1/*
2 * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30#ifndef __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__
31#define __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__
32
33#include <string>
34#include <vector>
35
36#include "base/hashmap.hh"
37#include "base/statistics.hh"
38#include "mem/protocol/CacheRequestType.hh"
39#include "mem/protocol/CacheResourceType.hh"
40#include "mem/protocol/RubyRequest.hh"
41#include "mem/ruby/common/DataBlock.hh"
42#include "mem/ruby/slicc_interface/AbstractCacheEntry.hh"
43#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
44#include "mem/ruby/structures/AbstractReplacementPolicy.hh"
45#include "mem/ruby/structures/BankedArray.hh"
46#include "mem/ruby/system/CacheRecorder.hh"
47#include "params/RubyCache.hh"
48#include "sim/sim_object.hh"
49
50class CacheMemory : public SimObject
51{
52 public:
53 typedef RubyCacheParams Params;
54 CacheMemory(const Params *p);
55 ~CacheMemory();
56
57 void init();
58
59 // Public Methods
60 // perform a cache access and see if we hit or not. Return true on a hit.
61 bool tryCacheAccess(const Address& address, RubyRequestType type,
62 DataBlock*& data_ptr);
63
64 // similar to above, but doesn't require full access check
65 bool testCacheAccess(const Address& address, RubyRequestType type,
66 DataBlock*& data_ptr);
67
68 // tests to see if an address is present in the cache
69 bool isTagPresent(const Address& address) const;
70
71 // Returns true if there is:
72 // a) a tag match on this address or there is
73 // b) an unused line in the same cache "way"
74 bool cacheAvail(const Address& address) const;
75
76 // find an unused entry and sets the tag appropriate for the address
77 AbstractCacheEntry* allocate(const Address& address,
78 AbstractCacheEntry* new_entry, bool touch);
79 AbstractCacheEntry* allocate(const Address& address,
80 AbstractCacheEntry* new_entry)
81 {
82 return allocate(address, new_entry, true);
83 }
84 void allocateVoid(const Address& address, AbstractCacheEntry* new_entry)
85 {
86 allocate(address, new_entry, true);
87 }
88
89 // Explicitly free up this address
90 void deallocate(const Address& address);
91
92 // Returns with the physical address of the conflicting cache line
93 Address cacheProbe(const Address& address) const;
94
95 // looks an address up in the cache
96 AbstractCacheEntry* lookup(const Address& address);
97 const AbstractCacheEntry* lookup(const Address& address) const;
98
99 Cycles getLatency() const { return m_latency; }
100 Cycles getTagLatency() const { return tagArray.getLatency(); }
101 Cycles getDataLatency() const { return dataArray.getLatency(); }
102
103
104 // Hook for checkpointing the contents of the cache
105 void recordCacheContents(int cntrl, CacheRecorder* tr) const;
106
107 // Set this address to most recently used
108 void setMRU(const Address& address);
109
110 void setLocked (const Address& addr, int context);
111 void clearLocked (const Address& addr);
112 bool isLocked (const Address& addr, int context);
113
114 // Print cache contents
115 void print(std::ostream& out) const;
116 void printData(std::ostream& out) const;
117
118 void regStats();
119 bool checkResourceAvailable(CacheResourceType res, Address addr);
| 1/*
2 * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30#ifndef __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__
31#define __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__
32
33#include <string>
34#include <vector>
35
36#include "base/hashmap.hh"
37#include "base/statistics.hh"
38#include "mem/protocol/CacheRequestType.hh"
39#include "mem/protocol/CacheResourceType.hh"
40#include "mem/protocol/RubyRequest.hh"
41#include "mem/ruby/common/DataBlock.hh"
42#include "mem/ruby/slicc_interface/AbstractCacheEntry.hh"
43#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
44#include "mem/ruby/structures/AbstractReplacementPolicy.hh"
45#include "mem/ruby/structures/BankedArray.hh"
46#include "mem/ruby/system/CacheRecorder.hh"
47#include "params/RubyCache.hh"
48#include "sim/sim_object.hh"
49
50class CacheMemory : public SimObject
51{
52 public:
53 typedef RubyCacheParams Params;
54 CacheMemory(const Params *p);
55 ~CacheMemory();
56
57 void init();
58
59 // Public Methods
60 // perform a cache access and see if we hit or not. Return true on a hit.
61 bool tryCacheAccess(const Address& address, RubyRequestType type,
62 DataBlock*& data_ptr);
63
64 // similar to above, but doesn't require full access check
65 bool testCacheAccess(const Address& address, RubyRequestType type,
66 DataBlock*& data_ptr);
67
68 // tests to see if an address is present in the cache
69 bool isTagPresent(const Address& address) const;
70
71 // Returns true if there is:
72 // a) a tag match on this address or there is
73 // b) an unused line in the same cache "way"
74 bool cacheAvail(const Address& address) const;
75
76 // find an unused entry and sets the tag appropriate for the address
77 AbstractCacheEntry* allocate(const Address& address,
78 AbstractCacheEntry* new_entry, bool touch);
79 AbstractCacheEntry* allocate(const Address& address,
80 AbstractCacheEntry* new_entry)
81 {
82 return allocate(address, new_entry, true);
83 }
84 void allocateVoid(const Address& address, AbstractCacheEntry* new_entry)
85 {
86 allocate(address, new_entry, true);
87 }
88
89 // Explicitly free up this address
90 void deallocate(const Address& address);
91
92 // Returns with the physical address of the conflicting cache line
93 Address cacheProbe(const Address& address) const;
94
95 // looks an address up in the cache
96 AbstractCacheEntry* lookup(const Address& address);
97 const AbstractCacheEntry* lookup(const Address& address) const;
98
99 Cycles getLatency() const { return m_latency; }
100 Cycles getTagLatency() const { return tagArray.getLatency(); }
101 Cycles getDataLatency() const { return dataArray.getLatency(); }
102
103
104 // Hook for checkpointing the contents of the cache
105 void recordCacheContents(int cntrl, CacheRecorder* tr) const;
106
107 // Set this address to most recently used
108 void setMRU(const Address& address);
109
110 void setLocked (const Address& addr, int context);
111 void clearLocked (const Address& addr);
112 bool isLocked (const Address& addr, int context);
113
114 // Print cache contents
115 void print(std::ostream& out) const;
116 void printData(std::ostream& out) const;
117
118 void regStats();
119 bool checkResourceAvailable(CacheResourceType res, Address addr);
|
121
122 public:
123 Stats::Scalar m_demand_hits;
124 Stats::Scalar m_demand_misses;
125 Stats::Formula m_demand_accesses;
126
127 Stats::Scalar m_sw_prefetches;
128 Stats::Scalar m_hw_prefetches;
129 Stats::Formula m_prefetches;
130
131 Stats::Vector m_accessModeType;
132
133 Stats::Scalar numDataArrayReads;
134 Stats::Scalar numDataArrayWrites;
135 Stats::Scalar numTagArrayReads;
136 Stats::Scalar numTagArrayWrites;
137
138 Stats::Scalar numTagArrayStalls;
139 Stats::Scalar numDataArrayStalls;
140
141 int getCacheSize() const { return m_cache_size; }
142 int getNumBlocks() const { return m_cache_num_sets * m_cache_assoc; }
143 Address getAddressAtIdx(int idx) const;
144
145 private:
146 // convert a Address to its location in the cache
147 int64 addressToCacheSet(const Address& address) const;
148
149 // Given a cache tag: returns the index of the tag in a set.
150 // returns -1 if the tag is not found.
151 int findTagInSet(int64 line, const Address& tag) const;
152 int findTagInSetIgnorePermissions(int64 cacheSet,
153 const Address& tag) const;
154
155 // Private copy constructor and assignment operator
156 CacheMemory(const CacheMemory& obj);
157 CacheMemory& operator=(const CacheMemory& obj);
158
159 private:
160 Cycles m_latency;
161
162 // Data Members (m_prefix)
163 bool m_is_instruction_only_cache;
164
165 // The first index is the # of cache lines.
166 // The second index is the the amount associativity.
167 m5::hash_map<Address, int> m_tag_index;
168 std::vector<std::vector<AbstractCacheEntry*> > m_cache;
169
170 AbstractReplacementPolicy *m_replacementPolicy_ptr;
171
172 BankedArray dataArray;
173 BankedArray tagArray;
174
175 int m_cache_size;
176 int m_cache_num_sets;
177 int m_cache_num_set_bits;
178 int m_cache_assoc;
179 int m_start_index_bit;
180 bool m_resource_stalls;
181};
182
183std::ostream& operator<<(std::ostream& out, const CacheMemory& obj);
184
185#endif // __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__
| 121
122 public:
123 Stats::Scalar m_demand_hits;
124 Stats::Scalar m_demand_misses;
125 Stats::Formula m_demand_accesses;
126
127 Stats::Scalar m_sw_prefetches;
128 Stats::Scalar m_hw_prefetches;
129 Stats::Formula m_prefetches;
130
131 Stats::Vector m_accessModeType;
132
133 Stats::Scalar numDataArrayReads;
134 Stats::Scalar numDataArrayWrites;
135 Stats::Scalar numTagArrayReads;
136 Stats::Scalar numTagArrayWrites;
137
138 Stats::Scalar numTagArrayStalls;
139 Stats::Scalar numDataArrayStalls;
140
141 int getCacheSize() const { return m_cache_size; }
142 int getNumBlocks() const { return m_cache_num_sets * m_cache_assoc; }
143 Address getAddressAtIdx(int idx) const;
144
145 private:
146 // convert a Address to its location in the cache
147 int64 addressToCacheSet(const Address& address) const;
148
149 // Given a cache tag: returns the index of the tag in a set.
150 // returns -1 if the tag is not found.
151 int findTagInSet(int64 line, const Address& tag) const;
152 int findTagInSetIgnorePermissions(int64 cacheSet,
153 const Address& tag) const;
154
155 // Private copy constructor and assignment operator
156 CacheMemory(const CacheMemory& obj);
157 CacheMemory& operator=(const CacheMemory& obj);
158
159 private:
160 Cycles m_latency;
161
162 // Data Members (m_prefix)
163 bool m_is_instruction_only_cache;
164
165 // The first index is the # of cache lines.
166 // The second index is the the amount associativity.
167 m5::hash_map<Address, int> m_tag_index;
168 std::vector<std::vector<AbstractCacheEntry*> > m_cache;
169
170 AbstractReplacementPolicy *m_replacementPolicy_ptr;
171
172 BankedArray dataArray;
173 BankedArray tagArray;
174
175 int m_cache_size;
176 int m_cache_num_sets;
177 int m_cache_num_set_bits;
178 int m_cache_assoc;
179 int m_start_index_bit;
180 bool m_resource_stalls;
181};
182
183std::ostream& operator<<(std::ostream& out, const CacheMemory& obj);
184
185#endif // __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__
|