CacheMemory.cc (10980:7de6f95a0817) CacheMemory.cc (11019:fc1e41e88fd3)
1/*
2 * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

--- 46 unchanged lines hidden (view full) ---

55CacheMemory::CacheMemory(const Params *p)
56 : SimObject(p),
57 dataArray(p->dataArrayBanks, p->dataAccessLatency,
58 p->start_index_bit, p->ruby_system),
59 tagArray(p->tagArrayBanks, p->tagAccessLatency,
60 p->start_index_bit, p->ruby_system)
61{
62 m_cache_size = p->size;
1/*
2 * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

--- 46 unchanged lines hidden (view full) ---

55CacheMemory::CacheMemory(const Params *p)
56 : SimObject(p),
57 dataArray(p->dataArrayBanks, p->dataAccessLatency,
58 p->start_index_bit, p->ruby_system),
59 tagArray(p->tagArrayBanks, p->tagAccessLatency,
60 p->start_index_bit, p->ruby_system)
61{
62 m_cache_size = p->size;
63 m_latency = p->latency;
64 m_cache_assoc = p->assoc;
65 m_replacementPolicy_ptr = p->replacement_policy;
66 m_replacementPolicy_ptr->setCache(this);
67 m_start_index_bit = p->start_index_bit;
68 m_is_instruction_only_cache = p->is_icache;
69 m_resource_stalls = p->resourceStalls;
70}
71

--- 536 unchanged lines hidden --- 		63 m_cache_assoc = p->assoc;
64 m_replacementPolicy_ptr = p->replacement_policy;
65 m_replacementPolicy_ptr->setCache(this);
66 m_start_index_bit = p->start_index_bit;
67 m_is_instruction_only_cache = p->is_icache;
68 m_resource_stalls = p->resourceStalls;
69}
70

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