CacheMemory.cc (10978:436d5dde4bb7) CacheMemory.cc (10980:7de6f95a0817)
1/*
2 * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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58 p->start_index_bit, p->ruby_system),
59 tagArray(p->tagArrayBanks, p->tagAccessLatency,
60 p->start_index_bit, p->ruby_system)
61{
62 m_cache_size = p->size;
63 m_latency = p->latency;
64 m_cache_assoc = p->assoc;
65 m_replacementPolicy_ptr = p->replacement_policy;
1/*
2 * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

--- 49 unchanged lines hidden (view full) ---

58 p->start_index_bit, p->ruby_system),
59 tagArray(p->tagArrayBanks, p->tagAccessLatency,
60 p->start_index_bit, p->ruby_system)
61{
62 m_cache_size = p->size;
63 m_latency = p->latency;
64 m_cache_assoc = p->assoc;
65 m_replacementPolicy_ptr = p->replacement_policy;
66 m_replacementPolicy_ptr->setCache(this);
66 m_start_index_bit = p->start_index_bit;
67 m_is_instruction_only_cache = p->is_icache;
68 m_resource_stalls = p->resourceStalls;
69}
70
71void
72CacheMemory::init()
73{

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587 numDataArrayStalls++;
588 return false;
589 }
590 } else {
591 assert(false);
592 return true;
593 }
594}
67 m_start_index_bit = p->start_index_bit;
68 m_is_instruction_only_cache = p->is_icache;
69 m_resource_stalls = p->resourceStalls;
70}
71
72void
73CacheMemory::init()
74{

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588 numDataArrayStalls++;
589 return false;
590 }
591 } else {
592 assert(false);
593 return true;
594 }
595}
596
597bool
598CacheMemory::isBlockInvalid(int64 cache_set, int64 loc)
599{
600 return (m_cache[cache_set][loc]->m_Permission == AccessPermission_Invalid);
601}
602
603bool
604CacheMemory::isBlockNotBusy(int64 cache_set, int64 loc)
605{
606 return (m_cache[cache_set][loc]->m_Permission != AccessPermission_Busy);
607}