1/* 2 * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 84 unchanged lines hidden (view full) --- 93 for (int i = 0; i < m_cache_num_sets; i++) { 94 for (int j = 0; j < m_cache_assoc; j++) { 95 delete m_cache[i][j]; 96 } 97 } 98} 99 100// convert a Address to its location in the cache |
101int64 |
102CacheMemory::addressToCacheSet(Addr address) const 103{ 104 assert(address == makeLineAddress(address)); 105 return bitSelect(address, m_start_index_bit, 106 m_start_index_bit + m_cache_num_set_bits - 1); 107} 108 109// Given a cache index: returns the index of the tag in a set. 110// returns -1 if the tag is not found. 111int |
112CacheMemory::findTagInSet(int64 cacheSet, Addr tag) const |
113{ 114 assert(tag == makeLineAddress(tag)); 115 // search the set for the tags 116 m5::hash_map<Addr, int>::const_iterator it = m_tag_index.find(tag); 117 if (it != m_tag_index.end()) 118 if (m_cache[cacheSet][it->second]->m_Permission != 119 AccessPermission_NotPresent) 120 return it->second; 121 return -1; // Not found 122} 123 124// Given a cache index: returns the index of the tag in a set. 125// returns -1 if the tag is not found. 126int |
127CacheMemory::findTagInSetIgnorePermissions(int64 cacheSet, |
128 Addr tag) const 129{ 130 assert(tag == makeLineAddress(tag)); 131 // search the set for the tags 132 m5::hash_map<Addr, int>::const_iterator it = m_tag_index.find(tag); 133 if (it != m_tag_index.end()) 134 return it->second; 135 return -1; // Not found --- 17 unchanged lines hidden (view full) --- 153 if (entry == NULL || 154 entry->m_Permission == AccessPermission_Invalid || 155 entry->m_Permission == AccessPermission_NotPresent) { 156 return tmp; 157 } 158 return entry->m_Address; 159} 160 |
161bool 162CacheMemory::tryCacheAccess(Addr address, RubyRequestType type, 163 DataBlock*& data_ptr) 164{ 165 assert(address == makeLineAddress(address)); 166 DPRINTF(RubyCache, "address: %s\n", address); 167 int64 cacheSet = addressToCacheSet(address); 168 int loc = findTagInSet(cacheSet, address); 169 if (loc != -1) { 170 // Do we even have a tag match? 171 AbstractCacheEntry* entry = m_cache[cacheSet][loc]; 172 m_replacementPolicy_ptr->touch(cacheSet, loc, curTick()); 173 data_ptr = &(entry->getDataBlk()); 174 175 if (entry->m_Permission == AccessPermission_Read_Write) { 176 return true; 177 } 178 if ((entry->m_Permission == AccessPermission_Read_Only) && 179 (type == RubyRequestType_LD || type == RubyRequestType_IFETCH)) { 180 return true; 181 } 182 // The line must not be accessible 183 } 184 data_ptr = NULL; 185 return false; 186} 187 188bool 189CacheMemory::testCacheAccess(Addr address, RubyRequestType type, 190 DataBlock*& data_ptr) 191{ 192 assert(address == makeLineAddress(address)); 193 DPRINTF(RubyCache, "address: %s\n", address); 194 int64 cacheSet = addressToCacheSet(address); 195 int loc = findTagInSet(cacheSet, address); 196 197 if (loc != -1) { 198 // Do we even have a tag match? 199 AbstractCacheEntry* entry = m_cache[cacheSet][loc]; 200 m_replacementPolicy_ptr->touch(cacheSet, loc, curTick()); 201 data_ptr = &(entry->getDataBlk()); 202 203 return m_cache[cacheSet][loc]->m_Permission != 204 AccessPermission_NotPresent; 205 } 206 207 data_ptr = NULL; 208 return false; 209} 210 |
211// tests to see if an address is present in the cache 212bool 213CacheMemory::isTagPresent(Addr address) const 214{ 215 assert(address == makeLineAddress(address)); |
216 int64 cacheSet = addressToCacheSet(address); |
217 int loc = findTagInSet(cacheSet, address); 218 219 if (loc == -1) { 220 // We didn't find the tag 221 DPRINTF(RubyCache, "No tag match for address: %s\n", address); 222 return false; 223 } 224 DPRINTF(RubyCache, "address: %s found\n", address); 225 return true; 226} 227 228// Returns true if there is: 229// a) a tag match on this address or there is 230// b) an unused line in the same cache "way" 231bool 232CacheMemory::cacheAvail(Addr address) const 233{ 234 assert(address == makeLineAddress(address)); 235 |
236 int64 cacheSet = addressToCacheSet(address); |
237 238 for (int i = 0; i < m_cache_assoc; i++) { 239 AbstractCacheEntry* entry = m_cache[cacheSet][i]; 240 if (entry != NULL) { 241 if (entry->m_Address == address || 242 entry->m_Permission == AccessPermission_NotPresent) { 243 // Already in the cache or we found an empty entry 244 return true; 245 } 246 } else { 247 return true; 248 } 249 } 250 return false; 251} 252 253AbstractCacheEntry* |
254CacheMemory::allocate(Addr address, AbstractCacheEntry* entry, bool touch) |
255{ 256 assert(address == makeLineAddress(address)); 257 assert(!isTagPresent(address)); 258 assert(cacheAvail(address)); 259 DPRINTF(RubyCache, "address: %s\n", address); 260 261 // Find the first open slot |
262 int64 cacheSet = addressToCacheSet(address); |
263 std::vector<AbstractCacheEntry*> &set = m_cache[cacheSet]; 264 for (int i = 0; i < m_cache_assoc; i++) { 265 if (!set[i] || set[i]->m_Permission == AccessPermission_NotPresent) { 266 set[i] = entry; // Init entry 267 set[i]->m_Address = address; 268 set[i]->m_Permission = AccessPermission_Invalid; 269 DPRINTF(RubyCache, "Allocate clearing lock for addr: %x\n", 270 address); 271 set[i]->m_locked = -1; 272 m_tag_index[address] = i; |
273 274 if (touch) { 275 m_replacementPolicy_ptr->touch(cacheSet, i, curTick()); 276 } 277 278 return entry; 279 } 280 } 281 panic("Allocate didn't find an available entry"); 282} 283 284void 285CacheMemory::deallocate(Addr address) 286{ 287 assert(address == makeLineAddress(address)); 288 assert(isTagPresent(address)); 289 DPRINTF(RubyCache, "address: %s\n", address); |
290 int64 cacheSet = addressToCacheSet(address); |
291 int loc = findTagInSet(cacheSet, address); 292 if (loc != -1) { 293 delete m_cache[cacheSet][loc]; 294 m_cache[cacheSet][loc] = NULL; 295 m_tag_index.erase(address); 296 } 297} 298 299// Returns with the physical address of the conflicting cache line 300Addr 301CacheMemory::cacheProbe(Addr address) const 302{ 303 assert(address == makeLineAddress(address)); 304 assert(!cacheAvail(address)); 305 |
306 int64 cacheSet = addressToCacheSet(address); |
307 return m_cache[cacheSet][m_replacementPolicy_ptr->getVictim(cacheSet)]-> 308 m_Address; 309} 310 311// looks an address up in the cache 312AbstractCacheEntry* 313CacheMemory::lookup(Addr address) 314{ 315 assert(address == makeLineAddress(address)); |
316 int64 cacheSet = addressToCacheSet(address); |
317 int loc = findTagInSet(cacheSet, address); 318 if(loc == -1) return NULL; 319 return m_cache[cacheSet][loc]; 320} 321 322// looks an address up in the cache 323const AbstractCacheEntry* 324CacheMemory::lookup(Addr address) const 325{ 326 assert(address == makeLineAddress(address)); |
327 int64 cacheSet = addressToCacheSet(address); |
328 int loc = findTagInSet(cacheSet, address); 329 if(loc == -1) return NULL; 330 return m_cache[cacheSet][loc]; 331} 332 333// Sets the most recently used bit for a cache block 334void 335CacheMemory::setMRU(Addr address) 336{ |
337 int64 cacheSet = addressToCacheSet(address); |
338 int loc = findTagInSet(cacheSet, address); 339 340 if(loc != -1) 341 m_replacementPolicy_ptr->touch(cacheSet, loc, curTick()); 342} 343 344void |
345CacheMemory::recordCacheContents(int cntrl, CacheRecorder* tr) const 346{ |
347 uint64 warmedUpBlocks = 0; 348 uint64 totalBlocks M5_VAR_USED = (uint64)m_cache_num_sets 349 * (uint64)m_cache_assoc; |
350 351 for (int i = 0; i < m_cache_num_sets; i++) { 352 for (int j = 0; j < m_cache_assoc; j++) { 353 if (m_cache[i][j] != NULL) { 354 AccessPermission perm = m_cache[i][j]->m_Permission; 355 RubyRequestType request_type = RubyRequestType_NULL; 356 if (perm == AccessPermission_Read_Only) { 357 if (m_is_instruction_only_cache) { --- 13 unchanged lines hidden (view full) --- 371 warmedUpBlocks++; 372 } 373 } 374 } 375 } 376 377 DPRINTF(RubyCacheTrace, "%s: %lli blocks of %lli total blocks" 378 "recorded %.2f%% \n", name().c_str(), warmedUpBlocks, |
379 (uint64)m_cache_num_sets * (uint64)m_cache_assoc, 380 (float(warmedUpBlocks)/float(totalBlocks))*100.0); |
381} 382 383void 384CacheMemory::print(ostream& out) const 385{ 386 out << "Cache dump: " << name() << endl; 387 for (int i = 0; i < m_cache_num_sets; i++) { 388 for (int j = 0; j < m_cache_assoc; j++) { --- 16 unchanged lines hidden (view full) --- 405 out << "printData() not supported" << endl; 406} 407 408void 409CacheMemory::setLocked(Addr address, int context) 410{ 411 DPRINTF(RubyCache, "Setting Lock for addr: %x to %d\n", address, context); 412 assert(address == makeLineAddress(address)); |
413 int64 cacheSet = addressToCacheSet(address); |
414 int loc = findTagInSet(cacheSet, address); 415 assert(loc != -1); |
416 m_cache[cacheSet][loc]->m_locked = context; |
417} 418 419void 420CacheMemory::clearLocked(Addr address) 421{ 422 DPRINTF(RubyCache, "Clear Lock for addr: %x\n", address); 423 assert(address == makeLineAddress(address)); |
424 int64 cacheSet = addressToCacheSet(address); |
425 int loc = findTagInSet(cacheSet, address); 426 assert(loc != -1); |
427 m_cache[cacheSet][loc]->m_locked = -1; |
428} 429 430bool 431CacheMemory::isLocked(Addr address, int context) 432{ 433 assert(address == makeLineAddress(address)); |
434 int64 cacheSet = addressToCacheSet(address); |
435 int loc = findTagInSet(cacheSet, address); 436 assert(loc != -1); 437 DPRINTF(RubyCache, "Testing Lock for addr: %llx cur %d con %d\n", 438 address, m_cache[cacheSet][loc]->m_locked, context); |
439 return m_cache[cacheSet][loc]->m_locked == context; |
440} 441 442void 443CacheMemory::regStats() 444{ 445 m_demand_hits 446 .name(name() + ".demand_hits") 447 .desc("Number of cache demand hits") --- 141 unchanged lines hidden (view full) --- 589 } 590 } else { 591 assert(false); 592 return true; 593 } 594} 595 596bool |
597CacheMemory::isBlockInvalid(int64 cache_set, int64 loc) |
598{ 599 return (m_cache[cache_set][loc]->m_Permission == AccessPermission_Invalid); 600} 601 602bool |
603CacheMemory::isBlockNotBusy(int64 cache_set, int64 loc) |
604{ 605 return (m_cache[cache_set][loc]->m_Permission != AccessPermission_Busy); 606} |