1/*
2 * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30#include "base/intmath.hh"
31#include "debug/RubyCache.hh"
32#include "debug/RubyCacheTrace.hh"
33#include "debug/RubyResourceStalls.hh"
34#include "debug/RubyStats.hh"
35#include "mem/protocol/AccessPermission.hh"
36#include "mem/ruby/structures/CacheMemory.hh"
37#include "mem/ruby/system/System.hh"
38
39using namespace std;
40
41ostream&
42operator<<(ostream& out, const CacheMemory& obj)
43{
44 obj.print(out);
45 out << flush;
46 return out;
47}
48
49CacheMemory *
50RubyCacheParams::create()
51{
52 return new CacheMemory(this);
53}
54
55CacheMemory::CacheMemory(const Params *p)
56 : SimObject(p),
57 dataArray(p->dataArrayBanks, p->dataAccessLatency,
58 p->start_index_bit, p->ruby_system),
59 tagArray(p->tagArrayBanks, p->tagAccessLatency,
60 p->start_index_bit, p->ruby_system)
61{
62 m_cache_size = p->size;
63 m_latency = p->latency;
64 m_cache_assoc = p->assoc;
65 m_replacementPolicy_ptr = p->replacement_policy;
66 m_start_index_bit = p->start_index_bit;
67 m_is_instruction_only_cache = p->is_icache;
68 m_resource_stalls = p->resourceStalls;
69}
70
71void
72CacheMemory::init()
73{
74 m_cache_num_sets = (m_cache_size / m_cache_assoc) /
75 RubySystem::getBlockSizeBytes();
76 assert(m_cache_num_sets > 1);
77 m_cache_num_set_bits = floorLog2(m_cache_num_sets);
78 assert(m_cache_num_set_bits > 0);
79
80 m_cache.resize(m_cache_num_sets);
81 for (int i = 0; i < m_cache_num_sets; i++) {
82 m_cache[i].resize(m_cache_assoc);
83 for (int j = 0; j < m_cache_assoc; j++) {
84 m_cache[i][j] = NULL;
85 }
86 }
87}
88
89CacheMemory::~CacheMemory()
90{
91 if (m_replacementPolicy_ptr != NULL)
92 delete m_replacementPolicy_ptr;
93 for (int i = 0; i < m_cache_num_sets; i++) {
94 for (int j = 0; j < m_cache_assoc; j++) {
95 delete m_cache[i][j];
96 }
97 }
98}
99
100// convert a Address to its location in the cache
101int64
102CacheMemory::addressToCacheSet(const Address& address) const
103{
104 assert(address == line_address(address));
105 return address.bitSelect(m_start_index_bit,
106 m_start_index_bit + m_cache_num_set_bits - 1);
107}
108
109// Given a cache index: returns the index of the tag in a set.
110// returns -1 if the tag is not found.
111int
112CacheMemory::findTagInSet(int64 cacheSet, const Address& tag) const
113{
114 assert(tag == line_address(tag));
115 // search the set for the tags
116 m5::hash_map<Address, int>::const_iterator it = m_tag_index.find(tag);
117 if (it != m_tag_index.end())
118 if (m_cache[cacheSet][it->second]->m_Permission !=
119 AccessPermission_NotPresent)
120 return it->second;
121 return -1; // Not found
122}
123
124// Given a cache index: returns the index of the tag in a set.
125// returns -1 if the tag is not found.
126int
127CacheMemory::findTagInSetIgnorePermissions(int64 cacheSet,
128 const Address& tag) const
129{
130 assert(tag == line_address(tag));
131 // search the set for the tags
132 m5::hash_map<Address, int>::const_iterator it = m_tag_index.find(tag);
133 if (it != m_tag_index.end())
134 return it->second;
135 return -1; // Not found
136}
137
138// Given an unique cache block identifier (idx): return the valid address
139// stored by the cache block. If the block is invalid/notpresent, the
140// function returns the 0 address
141Address
142CacheMemory::getAddressAtIdx(int idx) const
143{
144 Address tmp(0);
145
146 int set = idx / m_cache_assoc;
147 assert(set < m_cache_num_sets);
148
149 int way = idx - set * m_cache_assoc;
150 assert (way < m_cache_assoc);
151
152 AbstractCacheEntry* entry = m_cache[set][way];
153 if (entry == NULL ||
154 entry->m_Permission == AccessPermission_Invalid ||
155 entry->m_Permission == AccessPermission_NotPresent) {
156 return tmp;
157 }
158 return entry->m_Address;
159}
160
161bool
162CacheMemory::tryCacheAccess(const Address& address, RubyRequestType type,
163 DataBlock*& data_ptr)
164{
165 assert(address == line_address(address));
166 DPRINTF(RubyCache, "address: %s\n", address);
167 int64 cacheSet = addressToCacheSet(address);
168 int loc = findTagInSet(cacheSet, address);
169 if (loc != -1) {
170 // Do we even have a tag match?
171 AbstractCacheEntry* entry = m_cache[cacheSet][loc];
172 m_replacementPolicy_ptr->touch(cacheSet, loc, curTick());
173 data_ptr = &(entry->getDataBlk());
174
175 if (entry->m_Permission == AccessPermission_Read_Write) {
176 return true;
177 }
178 if ((entry->m_Permission == AccessPermission_Read_Only) &&
179 (type == RubyRequestType_LD || type == RubyRequestType_IFETCH)) {
180 return true;
181 }
182 // The line must not be accessible
183 }
184 data_ptr = NULL;
185 return false;
186}
187
188bool
189CacheMemory::testCacheAccess(const Address& address, RubyRequestType type,
190 DataBlock*& data_ptr)
191{
192 assert(address == line_address(address));
193 DPRINTF(RubyCache, "address: %s\n", address);
194 int64 cacheSet = addressToCacheSet(address);
195 int loc = findTagInSet(cacheSet, address);
196
197 if (loc != -1) {
198 // Do we even have a tag match?
199 AbstractCacheEntry* entry = m_cache[cacheSet][loc];
200 m_replacementPolicy_ptr->touch(cacheSet, loc, curTick());
201 data_ptr = &(entry->getDataBlk());
202
203 return m_cache[cacheSet][loc]->m_Permission !=
204 AccessPermission_NotPresent;
205 }
206
207 data_ptr = NULL;
208 return false;
209}
210
211// tests to see if an address is present in the cache
212bool
213CacheMemory::isTagPresent(const Address& address) const
214{
215 assert(address == line_address(address));
216 int64 cacheSet = addressToCacheSet(address);
217 int loc = findTagInSet(cacheSet, address);
218
219 if (loc == -1) {
220 // We didn't find the tag
221 DPRINTF(RubyCache, "No tag match for address: %s\n", address);
222 return false;
223 }
224 DPRINTF(RubyCache, "address: %s found\n", address);
225 return true;
226}
227
228// Returns true if there is:
229// a) a tag match on this address or there is
230// b) an unused line in the same cache "way"
231bool
232CacheMemory::cacheAvail(const Address& address) const
233{
234 assert(address == line_address(address));
235
236 int64 cacheSet = addressToCacheSet(address);
237
238 for (int i = 0; i < m_cache_assoc; i++) {
239 AbstractCacheEntry* entry = m_cache[cacheSet][i];
240 if (entry != NULL) {
241 if (entry->m_Address == address ||
242 entry->m_Permission == AccessPermission_NotPresent) {
243 // Already in the cache or we found an empty entry
244 return true;
245 }
246 } else {
247 return true;
248 }
249 }
250 return false;
251}
252
253AbstractCacheEntry*
254CacheMemory::allocate(const Address& address, AbstractCacheEntry* entry, bool touch)
255{
256 assert(address == line_address(address));
257 assert(!isTagPresent(address));
258 assert(cacheAvail(address));
259 DPRINTF(RubyCache, "address: %s\n", address);
260
261 // Find the first open slot
262 int64 cacheSet = addressToCacheSet(address);
263 std::vector<AbstractCacheEntry*> &set = m_cache[cacheSet];
264 for (int i = 0; i < m_cache_assoc; i++) {
265 if (!set[i] || set[i]->m_Permission == AccessPermission_NotPresent) {
266 set[i] = entry; // Init entry
267 set[i]->m_Address = address;
268 set[i]->m_Permission = AccessPermission_Invalid;
269 DPRINTF(RubyCache, "Allocate clearing lock for addr: %x\n",
270 address);
271 set[i]->m_locked = -1;
272 m_tag_index[address] = i;
273
274 if (touch) {
275 m_replacementPolicy_ptr->touch(cacheSet, i, curTick());
276 }
277
278 return entry;
279 }
280 }
281 panic("Allocate didn't find an available entry");
282}
283
284void
285CacheMemory::deallocate(const Address& address)
286{
287 assert(address == line_address(address));
288 assert(isTagPresent(address));
289 DPRINTF(RubyCache, "address: %s\n", address);
290 int64 cacheSet = addressToCacheSet(address);
291 int loc = findTagInSet(cacheSet, address);
292 if (loc != -1) {
293 delete m_cache[cacheSet][loc];
294 m_cache[cacheSet][loc] = NULL;
295 m_tag_index.erase(address);
296 }
297}
298
299// Returns with the physical address of the conflicting cache line
300Address
301CacheMemory::cacheProbe(const Address& address) const
302{
303 assert(address == line_address(address));
304 assert(!cacheAvail(address));
305
306 int64 cacheSet = addressToCacheSet(address);
307 return m_cache[cacheSet][m_replacementPolicy_ptr->getVictim(cacheSet)]->
308 m_Address;
309}
310
311// looks an address up in the cache
312AbstractCacheEntry*
313CacheMemory::lookup(const Address& address)
314{
315 assert(address == line_address(address));
316 int64 cacheSet = addressToCacheSet(address);
317 int loc = findTagInSet(cacheSet, address);
318 if(loc == -1) return NULL;
319 return m_cache[cacheSet][loc];
320}
321
322// looks an address up in the cache
323const AbstractCacheEntry*
324CacheMemory::lookup(const Address& address) const
325{
326 assert(address == line_address(address));
327 int64 cacheSet = addressToCacheSet(address);
328 int loc = findTagInSet(cacheSet, address);
329 if(loc == -1) return NULL;
330 return m_cache[cacheSet][loc];
331}
332
333// Sets the most recently used bit for a cache block
334void
335CacheMemory::setMRU(const Address& address)
336{
337 int64 cacheSet = addressToCacheSet(address);
338 int loc = findTagInSet(cacheSet, address);
339
340 if(loc != -1)
341 m_replacementPolicy_ptr->touch(cacheSet, loc, curTick());
342}
343
344void
345CacheMemory::recordCacheContents(int cntrl, CacheRecorder* tr) const
346{
347 uint64 warmedUpBlocks = 0;
348 uint64 totalBlocks M5_VAR_USED = (uint64)m_cache_num_sets
349 * (uint64)m_cache_assoc;
350
351 for (int i = 0; i < m_cache_num_sets; i++) {
352 for (int j = 0; j < m_cache_assoc; j++) {
353 if (m_cache[i][j] != NULL) {
354 AccessPermission perm = m_cache[i][j]->m_Permission;
355 RubyRequestType request_type = RubyRequestType_NULL;
356 if (perm == AccessPermission_Read_Only) {
357 if (m_is_instruction_only_cache) {
358 request_type = RubyRequestType_IFETCH;
359 } else {
360 request_type = RubyRequestType_LD;
361 }
362 } else if (perm == AccessPermission_Read_Write) {
363 request_type = RubyRequestType_ST;
364 }
365
366 if (request_type != RubyRequestType_NULL) {
367 tr->addRecord(cntrl, m_cache[i][j]->m_Address.getAddress(),
368 0, request_type,
369 m_replacementPolicy_ptr->getLastAccess(i, j),
370 m_cache[i][j]->getDataBlk());
371 warmedUpBlocks++;
372 }
373 }
374 }
375 }
376
377 DPRINTF(RubyCacheTrace, "%s: %lli blocks of %lli total blocks"
378 "recorded %.2f%% \n", name().c_str(), warmedUpBlocks,
379 (uint64)m_cache_num_sets * (uint64)m_cache_assoc,
380 (float(warmedUpBlocks)/float(totalBlocks))*100.0);
381}
382
383void
384CacheMemory::print(ostream& out) const
385{
386 out << "Cache dump: " << name() << endl;
387 for (int i = 0; i < m_cache_num_sets; i++) {
388 for (int j = 0; j < m_cache_assoc; j++) {
389 if (m_cache[i][j] != NULL) {
390 out << " Index: " << i
391 << " way: " << j
392 << " entry: " << *m_cache[i][j] << endl;
393 } else {
394 out << " Index: " << i
395 << " way: " << j
396 << " entry: NULL" << endl;
397 }
398 }
399 }
400}
401
402void
403CacheMemory::printData(ostream& out) const
404{
405 out << "printData() not supported" << endl;
406}
407
408void
409CacheMemory::setLocked(const Address& address, int context)
410{
411 DPRINTF(RubyCache, "Setting Lock for addr: %x to %d\n", address, context);
412 assert(address == line_address(address));
413 int64 cacheSet = addressToCacheSet(address);
414 int loc = findTagInSet(cacheSet, address);
415 assert(loc != -1);
416 m_cache[cacheSet][loc]->m_locked = context;
417}
418
419void
420CacheMemory::clearLocked(const Address& address)
421{
422 DPRINTF(RubyCache, "Clear Lock for addr: %x\n", address);
423 assert(address == line_address(address));
424 int64 cacheSet = addressToCacheSet(address);
425 int loc = findTagInSet(cacheSet, address);
426 assert(loc != -1);
427 m_cache[cacheSet][loc]->m_locked = -1;
428}
429
430bool
431CacheMemory::isLocked(const Address& address, int context)
432{
433 assert(address == line_address(address));
434 int64 cacheSet = addressToCacheSet(address);
435 int loc = findTagInSet(cacheSet, address);
436 assert(loc != -1);
437 DPRINTF(RubyCache, "Testing Lock for addr: %llx cur %d con %d\n",
438 address, m_cache[cacheSet][loc]->m_locked, context);
439 return m_cache[cacheSet][loc]->m_locked == context;
440}
441
442void
443CacheMemory::regStats()
444{
445 m_demand_hits
446 .name(name() + ".demand_hits")
447 .desc("Number of cache demand hits")
448 ;
449
450 m_demand_misses
451 .name(name() + ".demand_misses")
452 .desc("Number of cache demand misses")
453 ;
454
455 m_demand_accesses
456 .name(name() + ".demand_accesses")
457 .desc("Number of cache demand accesses")
458 ;
459
460 m_demand_accesses = m_demand_hits + m_demand_misses;
461
462 m_sw_prefetches
463 .name(name() + ".total_sw_prefetches")
464 .desc("Number of software prefetches")
465 .flags(Stats::nozero)
466 ;
467
468 m_hw_prefetches
469 .name(name() + ".total_hw_prefetches")
470 .desc("Number of hardware prefetches")
471 .flags(Stats::nozero)
472 ;
473
474 m_prefetches
475 .name(name() + ".total_prefetches")
476 .desc("Number of prefetches")
477 .flags(Stats::nozero)
478 ;
479
480 m_prefetches = m_sw_prefetches + m_hw_prefetches;
481
482 m_accessModeType
483 .init(RubyRequestType_NUM)
484 .name(name() + ".access_mode")
485 .flags(Stats::pdf | Stats::total)
486 ;
487 for (int i = 0; i < RubyAccessMode_NUM; i++) {
488 m_accessModeType
489 .subname(i, RubyAccessMode_to_string(RubyAccessMode(i)))
490 .flags(Stats::nozero)
491 ;
492 }
493
494 numDataArrayReads
495 .name(name() + ".num_data_array_reads")
496 .desc("number of data array reads")
497 .flags(Stats::nozero)
498 ;
499
500 numDataArrayWrites
501 .name(name() + ".num_data_array_writes")
502 .desc("number of data array writes")
503 .flags(Stats::nozero)
504 ;
505
506 numTagArrayReads
507 .name(name() + ".num_tag_array_reads")
508 .desc("number of tag array reads")
509 .flags(Stats::nozero)
510 ;
511
512 numTagArrayWrites
513 .name(name() + ".num_tag_array_writes")
514 .desc("number of tag array writes")
515 .flags(Stats::nozero)
516 ;
517
518 numTagArrayStalls
519 .name(name() + ".num_tag_array_stalls")
520 .desc("number of stalls caused by tag array")
521 .flags(Stats::nozero)
522 ;
523
524 numDataArrayStalls
525 .name(name() + ".num_data_array_stalls")
526 .desc("number of stalls caused by data array")
527 .flags(Stats::nozero)
528 ;
529}
530
| 1/*
2 * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30#include "base/intmath.hh"
31#include "debug/RubyCache.hh"
32#include "debug/RubyCacheTrace.hh"
33#include "debug/RubyResourceStalls.hh"
34#include "debug/RubyStats.hh"
35#include "mem/protocol/AccessPermission.hh"
36#include "mem/ruby/structures/CacheMemory.hh"
37#include "mem/ruby/system/System.hh"
38
39using namespace std;
40
41ostream&
42operator<<(ostream& out, const CacheMemory& obj)
43{
44 obj.print(out);
45 out << flush;
46 return out;
47}
48
49CacheMemory *
50RubyCacheParams::create()
51{
52 return new CacheMemory(this);
53}
54
55CacheMemory::CacheMemory(const Params *p)
56 : SimObject(p),
57 dataArray(p->dataArrayBanks, p->dataAccessLatency,
58 p->start_index_bit, p->ruby_system),
59 tagArray(p->tagArrayBanks, p->tagAccessLatency,
60 p->start_index_bit, p->ruby_system)
61{
62 m_cache_size = p->size;
63 m_latency = p->latency;
64 m_cache_assoc = p->assoc;
65 m_replacementPolicy_ptr = p->replacement_policy;
66 m_start_index_bit = p->start_index_bit;
67 m_is_instruction_only_cache = p->is_icache;
68 m_resource_stalls = p->resourceStalls;
69}
70
71void
72CacheMemory::init()
73{
74 m_cache_num_sets = (m_cache_size / m_cache_assoc) /
75 RubySystem::getBlockSizeBytes();
76 assert(m_cache_num_sets > 1);
77 m_cache_num_set_bits = floorLog2(m_cache_num_sets);
78 assert(m_cache_num_set_bits > 0);
79
80 m_cache.resize(m_cache_num_sets);
81 for (int i = 0; i < m_cache_num_sets; i++) {
82 m_cache[i].resize(m_cache_assoc);
83 for (int j = 0; j < m_cache_assoc; j++) {
84 m_cache[i][j] = NULL;
85 }
86 }
87}
88
89CacheMemory::~CacheMemory()
90{
91 if (m_replacementPolicy_ptr != NULL)
92 delete m_replacementPolicy_ptr;
93 for (int i = 0; i < m_cache_num_sets; i++) {
94 for (int j = 0; j < m_cache_assoc; j++) {
95 delete m_cache[i][j];
96 }
97 }
98}
99
100// convert a Address to its location in the cache
101int64
102CacheMemory::addressToCacheSet(const Address& address) const
103{
104 assert(address == line_address(address));
105 return address.bitSelect(m_start_index_bit,
106 m_start_index_bit + m_cache_num_set_bits - 1);
107}
108
109// Given a cache index: returns the index of the tag in a set.
110// returns -1 if the tag is not found.
111int
112CacheMemory::findTagInSet(int64 cacheSet, const Address& tag) const
113{
114 assert(tag == line_address(tag));
115 // search the set for the tags
116 m5::hash_map<Address, int>::const_iterator it = m_tag_index.find(tag);
117 if (it != m_tag_index.end())
118 if (m_cache[cacheSet][it->second]->m_Permission !=
119 AccessPermission_NotPresent)
120 return it->second;
121 return -1; // Not found
122}
123
124// Given a cache index: returns the index of the tag in a set.
125// returns -1 if the tag is not found.
126int
127CacheMemory::findTagInSetIgnorePermissions(int64 cacheSet,
128 const Address& tag) const
129{
130 assert(tag == line_address(tag));
131 // search the set for the tags
132 m5::hash_map<Address, int>::const_iterator it = m_tag_index.find(tag);
133 if (it != m_tag_index.end())
134 return it->second;
135 return -1; // Not found
136}
137
138// Given an unique cache block identifier (idx): return the valid address
139// stored by the cache block. If the block is invalid/notpresent, the
140// function returns the 0 address
141Address
142CacheMemory::getAddressAtIdx(int idx) const
143{
144 Address tmp(0);
145
146 int set = idx / m_cache_assoc;
147 assert(set < m_cache_num_sets);
148
149 int way = idx - set * m_cache_assoc;
150 assert (way < m_cache_assoc);
151
152 AbstractCacheEntry* entry = m_cache[set][way];
153 if (entry == NULL ||
154 entry->m_Permission == AccessPermission_Invalid ||
155 entry->m_Permission == AccessPermission_NotPresent) {
156 return tmp;
157 }
158 return entry->m_Address;
159}
160
161bool
162CacheMemory::tryCacheAccess(const Address& address, RubyRequestType type,
163 DataBlock*& data_ptr)
164{
165 assert(address == line_address(address));
166 DPRINTF(RubyCache, "address: %s\n", address);
167 int64 cacheSet = addressToCacheSet(address);
168 int loc = findTagInSet(cacheSet, address);
169 if (loc != -1) {
170 // Do we even have a tag match?
171 AbstractCacheEntry* entry = m_cache[cacheSet][loc];
172 m_replacementPolicy_ptr->touch(cacheSet, loc, curTick());
173 data_ptr = &(entry->getDataBlk());
174
175 if (entry->m_Permission == AccessPermission_Read_Write) {
176 return true;
177 }
178 if ((entry->m_Permission == AccessPermission_Read_Only) &&
179 (type == RubyRequestType_LD || type == RubyRequestType_IFETCH)) {
180 return true;
181 }
182 // The line must not be accessible
183 }
184 data_ptr = NULL;
185 return false;
186}
187
188bool
189CacheMemory::testCacheAccess(const Address& address, RubyRequestType type,
190 DataBlock*& data_ptr)
191{
192 assert(address == line_address(address));
193 DPRINTF(RubyCache, "address: %s\n", address);
194 int64 cacheSet = addressToCacheSet(address);
195 int loc = findTagInSet(cacheSet, address);
196
197 if (loc != -1) {
198 // Do we even have a tag match?
199 AbstractCacheEntry* entry = m_cache[cacheSet][loc];
200 m_replacementPolicy_ptr->touch(cacheSet, loc, curTick());
201 data_ptr = &(entry->getDataBlk());
202
203 return m_cache[cacheSet][loc]->m_Permission !=
204 AccessPermission_NotPresent;
205 }
206
207 data_ptr = NULL;
208 return false;
209}
210
211// tests to see if an address is present in the cache
212bool
213CacheMemory::isTagPresent(const Address& address) const
214{
215 assert(address == line_address(address));
216 int64 cacheSet = addressToCacheSet(address);
217 int loc = findTagInSet(cacheSet, address);
218
219 if (loc == -1) {
220 // We didn't find the tag
221 DPRINTF(RubyCache, "No tag match for address: %s\n", address);
222 return false;
223 }
224 DPRINTF(RubyCache, "address: %s found\n", address);
225 return true;
226}
227
228// Returns true if there is:
229// a) a tag match on this address or there is
230// b) an unused line in the same cache "way"
231bool
232CacheMemory::cacheAvail(const Address& address) const
233{
234 assert(address == line_address(address));
235
236 int64 cacheSet = addressToCacheSet(address);
237
238 for (int i = 0; i < m_cache_assoc; i++) {
239 AbstractCacheEntry* entry = m_cache[cacheSet][i];
240 if (entry != NULL) {
241 if (entry->m_Address == address ||
242 entry->m_Permission == AccessPermission_NotPresent) {
243 // Already in the cache or we found an empty entry
244 return true;
245 }
246 } else {
247 return true;
248 }
249 }
250 return false;
251}
252
253AbstractCacheEntry*
254CacheMemory::allocate(const Address& address, AbstractCacheEntry* entry, bool touch)
255{
256 assert(address == line_address(address));
257 assert(!isTagPresent(address));
258 assert(cacheAvail(address));
259 DPRINTF(RubyCache, "address: %s\n", address);
260
261 // Find the first open slot
262 int64 cacheSet = addressToCacheSet(address);
263 std::vector<AbstractCacheEntry*> &set = m_cache[cacheSet];
264 for (int i = 0; i < m_cache_assoc; i++) {
265 if (!set[i] || set[i]->m_Permission == AccessPermission_NotPresent) {
266 set[i] = entry; // Init entry
267 set[i]->m_Address = address;
268 set[i]->m_Permission = AccessPermission_Invalid;
269 DPRINTF(RubyCache, "Allocate clearing lock for addr: %x\n",
270 address);
271 set[i]->m_locked = -1;
272 m_tag_index[address] = i;
273
274 if (touch) {
275 m_replacementPolicy_ptr->touch(cacheSet, i, curTick());
276 }
277
278 return entry;
279 }
280 }
281 panic("Allocate didn't find an available entry");
282}
283
284void
285CacheMemory::deallocate(const Address& address)
286{
287 assert(address == line_address(address));
288 assert(isTagPresent(address));
289 DPRINTF(RubyCache, "address: %s\n", address);
290 int64 cacheSet = addressToCacheSet(address);
291 int loc = findTagInSet(cacheSet, address);
292 if (loc != -1) {
293 delete m_cache[cacheSet][loc];
294 m_cache[cacheSet][loc] = NULL;
295 m_tag_index.erase(address);
296 }
297}
298
299// Returns with the physical address of the conflicting cache line
300Address
301CacheMemory::cacheProbe(const Address& address) const
302{
303 assert(address == line_address(address));
304 assert(!cacheAvail(address));
305
306 int64 cacheSet = addressToCacheSet(address);
307 return m_cache[cacheSet][m_replacementPolicy_ptr->getVictim(cacheSet)]->
308 m_Address;
309}
310
311// looks an address up in the cache
312AbstractCacheEntry*
313CacheMemory::lookup(const Address& address)
314{
315 assert(address == line_address(address));
316 int64 cacheSet = addressToCacheSet(address);
317 int loc = findTagInSet(cacheSet, address);
318 if(loc == -1) return NULL;
319 return m_cache[cacheSet][loc];
320}
321
322// looks an address up in the cache
323const AbstractCacheEntry*
324CacheMemory::lookup(const Address& address) const
325{
326 assert(address == line_address(address));
327 int64 cacheSet = addressToCacheSet(address);
328 int loc = findTagInSet(cacheSet, address);
329 if(loc == -1) return NULL;
330 return m_cache[cacheSet][loc];
331}
332
333// Sets the most recently used bit for a cache block
334void
335CacheMemory::setMRU(const Address& address)
336{
337 int64 cacheSet = addressToCacheSet(address);
338 int loc = findTagInSet(cacheSet, address);
339
340 if(loc != -1)
341 m_replacementPolicy_ptr->touch(cacheSet, loc, curTick());
342}
343
344void
345CacheMemory::recordCacheContents(int cntrl, CacheRecorder* tr) const
346{
347 uint64 warmedUpBlocks = 0;
348 uint64 totalBlocks M5_VAR_USED = (uint64)m_cache_num_sets
349 * (uint64)m_cache_assoc;
350
351 for (int i = 0; i < m_cache_num_sets; i++) {
352 for (int j = 0; j < m_cache_assoc; j++) {
353 if (m_cache[i][j] != NULL) {
354 AccessPermission perm = m_cache[i][j]->m_Permission;
355 RubyRequestType request_type = RubyRequestType_NULL;
356 if (perm == AccessPermission_Read_Only) {
357 if (m_is_instruction_only_cache) {
358 request_type = RubyRequestType_IFETCH;
359 } else {
360 request_type = RubyRequestType_LD;
361 }
362 } else if (perm == AccessPermission_Read_Write) {
363 request_type = RubyRequestType_ST;
364 }
365
366 if (request_type != RubyRequestType_NULL) {
367 tr->addRecord(cntrl, m_cache[i][j]->m_Address.getAddress(),
368 0, request_type,
369 m_replacementPolicy_ptr->getLastAccess(i, j),
370 m_cache[i][j]->getDataBlk());
371 warmedUpBlocks++;
372 }
373 }
374 }
375 }
376
377 DPRINTF(RubyCacheTrace, "%s: %lli blocks of %lli total blocks"
378 "recorded %.2f%% \n", name().c_str(), warmedUpBlocks,
379 (uint64)m_cache_num_sets * (uint64)m_cache_assoc,
380 (float(warmedUpBlocks)/float(totalBlocks))*100.0);
381}
382
383void
384CacheMemory::print(ostream& out) const
385{
386 out << "Cache dump: " << name() << endl;
387 for (int i = 0; i < m_cache_num_sets; i++) {
388 for (int j = 0; j < m_cache_assoc; j++) {
389 if (m_cache[i][j] != NULL) {
390 out << " Index: " << i
391 << " way: " << j
392 << " entry: " << *m_cache[i][j] << endl;
393 } else {
394 out << " Index: " << i
395 << " way: " << j
396 << " entry: NULL" << endl;
397 }
398 }
399 }
400}
401
402void
403CacheMemory::printData(ostream& out) const
404{
405 out << "printData() not supported" << endl;
406}
407
408void
409CacheMemory::setLocked(const Address& address, int context)
410{
411 DPRINTF(RubyCache, "Setting Lock for addr: %x to %d\n", address, context);
412 assert(address == line_address(address));
413 int64 cacheSet = addressToCacheSet(address);
414 int loc = findTagInSet(cacheSet, address);
415 assert(loc != -1);
416 m_cache[cacheSet][loc]->m_locked = context;
417}
418
419void
420CacheMemory::clearLocked(const Address& address)
421{
422 DPRINTF(RubyCache, "Clear Lock for addr: %x\n", address);
423 assert(address == line_address(address));
424 int64 cacheSet = addressToCacheSet(address);
425 int loc = findTagInSet(cacheSet, address);
426 assert(loc != -1);
427 m_cache[cacheSet][loc]->m_locked = -1;
428}
429
430bool
431CacheMemory::isLocked(const Address& address, int context)
432{
433 assert(address == line_address(address));
434 int64 cacheSet = addressToCacheSet(address);
435 int loc = findTagInSet(cacheSet, address);
436 assert(loc != -1);
437 DPRINTF(RubyCache, "Testing Lock for addr: %llx cur %d con %d\n",
438 address, m_cache[cacheSet][loc]->m_locked, context);
439 return m_cache[cacheSet][loc]->m_locked == context;
440}
441
442void
443CacheMemory::regStats()
444{
445 m_demand_hits
446 .name(name() + ".demand_hits")
447 .desc("Number of cache demand hits")
448 ;
449
450 m_demand_misses
451 .name(name() + ".demand_misses")
452 .desc("Number of cache demand misses")
453 ;
454
455 m_demand_accesses
456 .name(name() + ".demand_accesses")
457 .desc("Number of cache demand accesses")
458 ;
459
460 m_demand_accesses = m_demand_hits + m_demand_misses;
461
462 m_sw_prefetches
463 .name(name() + ".total_sw_prefetches")
464 .desc("Number of software prefetches")
465 .flags(Stats::nozero)
466 ;
467
468 m_hw_prefetches
469 .name(name() + ".total_hw_prefetches")
470 .desc("Number of hardware prefetches")
471 .flags(Stats::nozero)
472 ;
473
474 m_prefetches
475 .name(name() + ".total_prefetches")
476 .desc("Number of prefetches")
477 .flags(Stats::nozero)
478 ;
479
480 m_prefetches = m_sw_prefetches + m_hw_prefetches;
481
482 m_accessModeType
483 .init(RubyRequestType_NUM)
484 .name(name() + ".access_mode")
485 .flags(Stats::pdf | Stats::total)
486 ;
487 for (int i = 0; i < RubyAccessMode_NUM; i++) {
488 m_accessModeType
489 .subname(i, RubyAccessMode_to_string(RubyAccessMode(i)))
490 .flags(Stats::nozero)
491 ;
492 }
493
494 numDataArrayReads
495 .name(name() + ".num_data_array_reads")
496 .desc("number of data array reads")
497 .flags(Stats::nozero)
498 ;
499
500 numDataArrayWrites
501 .name(name() + ".num_data_array_writes")
502 .desc("number of data array writes")
503 .flags(Stats::nozero)
504 ;
505
506 numTagArrayReads
507 .name(name() + ".num_tag_array_reads")
508 .desc("number of tag array reads")
509 .flags(Stats::nozero)
510 ;
511
512 numTagArrayWrites
513 .name(name() + ".num_tag_array_writes")
514 .desc("number of tag array writes")
515 .flags(Stats::nozero)
516 ;
517
518 numTagArrayStalls
519 .name(name() + ".num_tag_array_stalls")
520 .desc("number of stalls caused by tag array")
521 .flags(Stats::nozero)
522 ;
523
524 numDataArrayStalls
525 .name(name() + ".num_data_array_stalls")
526 .desc("number of stalls caused by data array")
527 .flags(Stats::nozero)
528 ;
529}
530
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