1/*
2 * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30#include "base/intmath.hh"
31#include "debug/RubyCache.hh"
32#include "debug/RubyCacheTrace.hh"
33#include "debug/RubyResourceStalls.hh"
34#include "debug/RubyStats.hh"
35#include "mem/protocol/AccessPermission.hh"
36#include "mem/ruby/structures/CacheMemory.hh"
37#include "mem/ruby/system/System.hh"
38
39using namespace std;
40
41ostream&
42operator<<(ostream& out, const CacheMemory& obj)
43{
44 obj.print(out);
45 out << flush;
46 return out;
47}
48
49CacheMemory *
50RubyCacheParams::create()
51{
52 return new CacheMemory(this);
53}
54
55CacheMemory::CacheMemory(const Params *p)
56 : SimObject(p),
57 dataArray(p->dataArrayBanks, p->dataAccessLatency,
58 p->start_index_bit, p->ruby_system),
59 tagArray(p->tagArrayBanks, p->tagAccessLatency,
60 p->start_index_bit, p->ruby_system)
61{
62 m_cache_size = p->size;
63 m_latency = p->latency;
64 m_cache_assoc = p->assoc;
65 m_replacementPolicy_ptr = p->replacement_policy;
66 m_replacementPolicy_ptr->setCache(this);
67 m_start_index_bit = p->start_index_bit;
68 m_is_instruction_only_cache = p->is_icache;
69 m_resource_stalls = p->resourceStalls;
70}
71
72void
73CacheMemory::init()
74{
75 m_cache_num_sets = (m_cache_size / m_cache_assoc) /
76 RubySystem::getBlockSizeBytes();
77 assert(m_cache_num_sets > 1);
78 m_cache_num_set_bits = floorLog2(m_cache_num_sets);
79 assert(m_cache_num_set_bits > 0);
80
81 m_cache.resize(m_cache_num_sets);
82 for (int i = 0; i < m_cache_num_sets; i++) {
83 m_cache[i].resize(m_cache_assoc);
84 for (int j = 0; j < m_cache_assoc; j++) {
85 m_cache[i][j] = NULL;
86 }
87 }
88}
89
90CacheMemory::~CacheMemory()
91{
92 if (m_replacementPolicy_ptr != NULL)
93 delete m_replacementPolicy_ptr;
94 for (int i = 0; i < m_cache_num_sets; i++) {
95 for (int j = 0; j < m_cache_assoc; j++) {
96 delete m_cache[i][j];
97 }
98 }
99}
100
101// convert a Address to its location in the cache
102int64
103CacheMemory::addressToCacheSet(const Address& address) const
104{
105 assert(address == line_address(address));
106 return address.bitSelect(m_start_index_bit,
107 m_start_index_bit + m_cache_num_set_bits - 1);
108}
109
110// Given a cache index: returns the index of the tag in a set.
111// returns -1 if the tag is not found.
112int
113CacheMemory::findTagInSet(int64 cacheSet, const Address& tag) const
114{
115 assert(tag == line_address(tag));
116 // search the set for the tags
117 m5::hash_map<Address, int>::const_iterator it = m_tag_index.find(tag);
118 if (it != m_tag_index.end())
119 if (m_cache[cacheSet][it->second]->m_Permission !=
120 AccessPermission_NotPresent)
121 return it->second;
122 return -1; // Not found
123}
124
125// Given a cache index: returns the index of the tag in a set.
126// returns -1 if the tag is not found.
127int
128CacheMemory::findTagInSetIgnorePermissions(int64 cacheSet,
129 const Address& tag) const
130{
131 assert(tag == line_address(tag));
132 // search the set for the tags
133 m5::hash_map<Address, int>::const_iterator it = m_tag_index.find(tag);
134 if (it != m_tag_index.end())
135 return it->second;
136 return -1; // Not found
137}
138
139// Given an unique cache block identifier (idx): return the valid address
140// stored by the cache block. If the block is invalid/notpresent, the
141// function returns the 0 address
142Address
143CacheMemory::getAddressAtIdx(int idx) const
144{
145 Address tmp(0);
146
147 int set = idx / m_cache_assoc;
148 assert(set < m_cache_num_sets);
149
150 int way = idx - set * m_cache_assoc;
151 assert (way < m_cache_assoc);
152
153 AbstractCacheEntry* entry = m_cache[set][way];
154 if (entry == NULL ||
155 entry->m_Permission == AccessPermission_Invalid ||
156 entry->m_Permission == AccessPermission_NotPresent) {
157 return tmp;
158 }
159 return entry->m_Address;
160}
161
162bool
163CacheMemory::tryCacheAccess(const Address& address, RubyRequestType type,
164 DataBlock*& data_ptr)
165{
166 assert(address == line_address(address));
167 DPRINTF(RubyCache, "address: %s\n", address);
168 int64 cacheSet = addressToCacheSet(address);
169 int loc = findTagInSet(cacheSet, address);
170 if (loc != -1) {
171 // Do we even have a tag match?
172 AbstractCacheEntry* entry = m_cache[cacheSet][loc];
173 m_replacementPolicy_ptr->touch(cacheSet, loc, curTick());
174 data_ptr = &(entry->getDataBlk());
175
176 if (entry->m_Permission == AccessPermission_Read_Write) {
177 return true;
178 }
179 if ((entry->m_Permission == AccessPermission_Read_Only) &&
180 (type == RubyRequestType_LD || type == RubyRequestType_IFETCH)) {
181 return true;
182 }
183 // The line must not be accessible
184 }
185 data_ptr = NULL;
186 return false;
187}
188
189bool
190CacheMemory::testCacheAccess(const Address& address, RubyRequestType type,
191 DataBlock*& data_ptr)
192{
193 assert(address == line_address(address));
194 DPRINTF(RubyCache, "address: %s\n", address);
195 int64 cacheSet = addressToCacheSet(address);
196 int loc = findTagInSet(cacheSet, address);
197
198 if (loc != -1) {
199 // Do we even have a tag match?
200 AbstractCacheEntry* entry = m_cache[cacheSet][loc];
201 m_replacementPolicy_ptr->touch(cacheSet, loc, curTick());
202 data_ptr = &(entry->getDataBlk());
203
204 return m_cache[cacheSet][loc]->m_Permission !=
205 AccessPermission_NotPresent;
206 }
207
208 data_ptr = NULL;
209 return false;
210}
211
212// tests to see if an address is present in the cache
213bool
214CacheMemory::isTagPresent(const Address& address) const
215{
216 assert(address == line_address(address));
217 int64 cacheSet = addressToCacheSet(address);
218 int loc = findTagInSet(cacheSet, address);
219
220 if (loc == -1) {
221 // We didn't find the tag
222 DPRINTF(RubyCache, "No tag match for address: %s\n", address);
223 return false;
224 }
225 DPRINTF(RubyCache, "address: %s found\n", address);
226 return true;
227}
228
229// Returns true if there is:
230// a) a tag match on this address or there is
231// b) an unused line in the same cache "way"
232bool
233CacheMemory::cacheAvail(const Address& address) const
234{
235 assert(address == line_address(address));
236
237 int64 cacheSet = addressToCacheSet(address);
238
239 for (int i = 0; i < m_cache_assoc; i++) {
240 AbstractCacheEntry* entry = m_cache[cacheSet][i];
241 if (entry != NULL) {
242 if (entry->m_Address == address ||
243 entry->m_Permission == AccessPermission_NotPresent) {
244 // Already in the cache or we found an empty entry
245 return true;
246 }
247 } else {
248 return true;
249 }
250 }
251 return false;
252}
253
254AbstractCacheEntry*
255CacheMemory::allocate(const Address& address, AbstractCacheEntry* entry, bool touch)
256{
257 assert(address == line_address(address));
258 assert(!isTagPresent(address));
259 assert(cacheAvail(address));
260 DPRINTF(RubyCache, "address: %s\n", address);
261
262 // Find the first open slot
263 int64 cacheSet = addressToCacheSet(address);
264 std::vector<AbstractCacheEntry*> &set = m_cache[cacheSet];
265 for (int i = 0; i < m_cache_assoc; i++) {
266 if (!set[i] || set[i]->m_Permission == AccessPermission_NotPresent) {
267 set[i] = entry; // Init entry
268 set[i]->m_Address = address;
269 set[i]->m_Permission = AccessPermission_Invalid;
270 DPRINTF(RubyCache, "Allocate clearing lock for addr: %x\n",
271 address);
272 set[i]->m_locked = -1;
273 m_tag_index[address] = i;
274
275 if (touch) {
276 m_replacementPolicy_ptr->touch(cacheSet, i, curTick());
277 }
278
279 return entry;
280 }
281 }
282 panic("Allocate didn't find an available entry");
283}
284
285void
286CacheMemory::deallocate(const Address& address)
287{
288 assert(address == line_address(address));
289 assert(isTagPresent(address));
290 DPRINTF(RubyCache, "address: %s\n", address);
291 int64 cacheSet = addressToCacheSet(address);
292 int loc = findTagInSet(cacheSet, address);
293 if (loc != -1) {
294 delete m_cache[cacheSet][loc];
295 m_cache[cacheSet][loc] = NULL;
296 m_tag_index.erase(address);
297 }
298}
299
300// Returns with the physical address of the conflicting cache line
301Address
302CacheMemory::cacheProbe(const Address& address) const
303{
304 assert(address == line_address(address));
305 assert(!cacheAvail(address));
306
307 int64 cacheSet = addressToCacheSet(address);
308 return m_cache[cacheSet][m_replacementPolicy_ptr->getVictim(cacheSet)]->
309 m_Address;
310}
311
312// looks an address up in the cache
313AbstractCacheEntry*
314CacheMemory::lookup(const Address& address)
315{
316 assert(address == line_address(address));
317 int64 cacheSet = addressToCacheSet(address);
318 int loc = findTagInSet(cacheSet, address);
319 if(loc == -1) return NULL;
320 return m_cache[cacheSet][loc];
321}
322
323// looks an address up in the cache
324const AbstractCacheEntry*
325CacheMemory::lookup(const Address& address) const
326{
327 assert(address == line_address(address));
328 int64 cacheSet = addressToCacheSet(address);
329 int loc = findTagInSet(cacheSet, address);
330 if(loc == -1) return NULL;
331 return m_cache[cacheSet][loc];
332}
333
334// Sets the most recently used bit for a cache block
335void
336CacheMemory::setMRU(const Address& address)
337{
338 int64 cacheSet = addressToCacheSet(address);
339 int loc = findTagInSet(cacheSet, address);
340
341 if(loc != -1)
342 m_replacementPolicy_ptr->touch(cacheSet, loc, curTick());
343}
344
345void
346CacheMemory::recordCacheContents(int cntrl, CacheRecorder* tr) const
347{
348 uint64 warmedUpBlocks = 0;
349 uint64 totalBlocks M5_VAR_USED = (uint64)m_cache_num_sets
350 * (uint64)m_cache_assoc;
351
352 for (int i = 0; i < m_cache_num_sets; i++) {
353 for (int j = 0; j < m_cache_assoc; j++) {
354 if (m_cache[i][j] != NULL) {
355 AccessPermission perm = m_cache[i][j]->m_Permission;
356 RubyRequestType request_type = RubyRequestType_NULL;
357 if (perm == AccessPermission_Read_Only) {
358 if (m_is_instruction_only_cache) {
359 request_type = RubyRequestType_IFETCH;
360 } else {
361 request_type = RubyRequestType_LD;
362 }
363 } else if (perm == AccessPermission_Read_Write) {
364 request_type = RubyRequestType_ST;
365 }
366
367 if (request_type != RubyRequestType_NULL) {
368 tr->addRecord(cntrl, m_cache[i][j]->m_Address.getAddress(),
369 0, request_type,
370 m_replacementPolicy_ptr->getLastAccess(i, j),
371 m_cache[i][j]->getDataBlk());
372 warmedUpBlocks++;
373 }
374 }
375 }
376 }
377
378 DPRINTF(RubyCacheTrace, "%s: %lli blocks of %lli total blocks"
379 "recorded %.2f%% \n", name().c_str(), warmedUpBlocks,
380 (uint64)m_cache_num_sets * (uint64)m_cache_assoc,
381 (float(warmedUpBlocks)/float(totalBlocks))*100.0);
382}
383
384void
385CacheMemory::print(ostream& out) const
386{
387 out << "Cache dump: " << name() << endl;
388 for (int i = 0; i < m_cache_num_sets; i++) {
389 for (int j = 0; j < m_cache_assoc; j++) {
390 if (m_cache[i][j] != NULL) {
391 out << " Index: " << i
392 << " way: " << j
393 << " entry: " << *m_cache[i][j] << endl;
394 } else {
395 out << " Index: " << i
396 << " way: " << j
397 << " entry: NULL" << endl;
398 }
399 }
400 }
401}
402
403void
404CacheMemory::printData(ostream& out) const
405{
406 out << "printData() not supported" << endl;
407}
408
409void
410CacheMemory::setLocked(const Address& address, int context)
411{
412 DPRINTF(RubyCache, "Setting Lock for addr: %x to %d\n", address, context);
413 assert(address == line_address(address));
414 int64 cacheSet = addressToCacheSet(address);
415 int loc = findTagInSet(cacheSet, address);
416 assert(loc != -1);
417 m_cache[cacheSet][loc]->m_locked = context;
418}
419
420void
421CacheMemory::clearLocked(const Address& address)
422{
423 DPRINTF(RubyCache, "Clear Lock for addr: %x\n", address);
424 assert(address == line_address(address));
425 int64 cacheSet = addressToCacheSet(address);
426 int loc = findTagInSet(cacheSet, address);
427 assert(loc != -1);
428 m_cache[cacheSet][loc]->m_locked = -1;
429}
430
431bool
432CacheMemory::isLocked(const Address& address, int context)
433{
434 assert(address == line_address(address));
435 int64 cacheSet = addressToCacheSet(address);
436 int loc = findTagInSet(cacheSet, address);
437 assert(loc != -1);
438 DPRINTF(RubyCache, "Testing Lock for addr: %llx cur %d con %d\n",
439 address, m_cache[cacheSet][loc]->m_locked, context);
440 return m_cache[cacheSet][loc]->m_locked == context;
441}
442
443void
444CacheMemory::regStats()
445{
446 m_demand_hits
447 .name(name() + ".demand_hits")
448 .desc("Number of cache demand hits")
449 ;
450
451 m_demand_misses
452 .name(name() + ".demand_misses")
453 .desc("Number of cache demand misses")
454 ;
455
456 m_demand_accesses
457 .name(name() + ".demand_accesses")
458 .desc("Number of cache demand accesses")
459 ;
460
461 m_demand_accesses = m_demand_hits + m_demand_misses;
462
463 m_sw_prefetches
464 .name(name() + ".total_sw_prefetches")
465 .desc("Number of software prefetches")
466 .flags(Stats::nozero)
467 ;
468
469 m_hw_prefetches
470 .name(name() + ".total_hw_prefetches")
471 .desc("Number of hardware prefetches")
472 .flags(Stats::nozero)
473 ;
474
475 m_prefetches
476 .name(name() + ".total_prefetches")
477 .desc("Number of prefetches")
478 .flags(Stats::nozero)
479 ;
480
481 m_prefetches = m_sw_prefetches + m_hw_prefetches;
482
483 m_accessModeType
484 .init(RubyRequestType_NUM)
485 .name(name() + ".access_mode")
486 .flags(Stats::pdf | Stats::total)
487 ;
488 for (int i = 0; i < RubyAccessMode_NUM; i++) {
489 m_accessModeType
490 .subname(i, RubyAccessMode_to_string(RubyAccessMode(i)))
491 .flags(Stats::nozero)
492 ;
493 }
494
495 numDataArrayReads
496 .name(name() + ".num_data_array_reads")
497 .desc("number of data array reads")
498 .flags(Stats::nozero)
499 ;
500
501 numDataArrayWrites
502 .name(name() + ".num_data_array_writes")
503 .desc("number of data array writes")
504 .flags(Stats::nozero)
505 ;
506
507 numTagArrayReads
508 .name(name() + ".num_tag_array_reads")
509 .desc("number of tag array reads")
510 .flags(Stats::nozero)
511 ;
512
513 numTagArrayWrites
514 .name(name() + ".num_tag_array_writes")
515 .desc("number of tag array writes")
516 .flags(Stats::nozero)
517 ;
518
519 numTagArrayStalls
520 .name(name() + ".num_tag_array_stalls")
521 .desc("number of stalls caused by tag array")
522 .flags(Stats::nozero)
523 ;
524
525 numDataArrayStalls
526 .name(name() + ".num_data_array_stalls")
527 .desc("number of stalls caused by data array")
528 .flags(Stats::nozero)
529 ;
530}
531
532// assumption: SLICC generated files will only call this function
533// once **all** resources are granted
534void
535CacheMemory::recordRequestType(CacheRequestType requestType, Address addr)
536{
537 DPRINTF(RubyStats, "Recorded statistic: %s\n",
538 CacheRequestType_to_string(requestType));
539 switch(requestType) {
540 case CacheRequestType_DataArrayRead:
541 if (m_resource_stalls)
542 dataArray.reserve(addressToCacheSet(addr));
543 numDataArrayReads++;
544 return;
545 case CacheRequestType_DataArrayWrite:
546 if (m_resource_stalls)
547 dataArray.reserve(addressToCacheSet(addr));
548 numDataArrayWrites++;
549 return;
550 case CacheRequestType_TagArrayRead:
551 if (m_resource_stalls)
552 tagArray.reserve(addressToCacheSet(addr));
553 numTagArrayReads++;
554 return;
555 case CacheRequestType_TagArrayWrite:
556 if (m_resource_stalls)
557 tagArray.reserve(addressToCacheSet(addr));
558 numTagArrayWrites++;
559 return;
560 default:
561 warn("CacheMemory access_type not found: %s",
562 CacheRequestType_to_string(requestType));
563 }
564}
565
566bool
567CacheMemory::checkResourceAvailable(CacheResourceType res, Address addr)
568{
569 if (!m_resource_stalls) {
570 return true;
571 }
572
573 if (res == CacheResourceType_TagArray) {
574 if (tagArray.tryAccess(addressToCacheSet(addr))) return true;
575 else {
576 DPRINTF(RubyResourceStalls,
577 "Tag array stall on addr %s in set %d\n",
578 addr, addressToCacheSet(addr));
579 numTagArrayStalls++;
580 return false;
581 }
582 } else if (res == CacheResourceType_DataArray) {
583 if (dataArray.tryAccess(addressToCacheSet(addr))) return true;
584 else {
585 DPRINTF(RubyResourceStalls,
586 "Data array stall on addr %s in set %d\n",
587 addr, addressToCacheSet(addr));
588 numDataArrayStalls++;
589 return false;
590 }
591 } else {
592 assert(false);
593 return true;
594 }
595}
596
597bool
598CacheMemory::isBlockInvalid(int64 cache_set, int64 loc)
599{
600 return (m_cache[cache_set][loc]->m_Permission == AccessPermission_Invalid);
601}
602
603bool
604CacheMemory::isBlockNotBusy(int64 cache_set, int64 loc)
605{
606 return (m_cache[cache_set][loc]->m_Permission != AccessPermission_Busy);
607}