BankedArray.hh (11061:25b53a7195f7) | BankedArray.hh (11108:6342ddf6d733) |
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1/* 2 * Copyright (c) 2012 Advanced Micro Devices, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 21 unchanged lines hidden (view full) --- 30 */ 31 32#ifndef __MEM_RUBY_STRUCTURES_BANKEDARRAY_HH__ 33#define __MEM_RUBY_STRUCTURES_BANKEDARRAY_HH__ 34 35#include <vector> 36 37#include "mem/ruby/common/TypeDefines.hh" | 1/* 2 * Copyright (c) 2012 Advanced Micro Devices, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 21 unchanged lines hidden (view full) --- 30 */ 31 32#ifndef __MEM_RUBY_STRUCTURES_BANKEDARRAY_HH__ 33#define __MEM_RUBY_STRUCTURES_BANKEDARRAY_HH__ 34 35#include <vector> 36 37#include "mem/ruby/common/TypeDefines.hh" |
38#include "mem/ruby/system/System.hh" | 38#include "mem/ruby/system/RubySystem.hh" |
39#include "sim/core.hh" 40 41class BankedArray 42{ 43 private: 44 unsigned int banks; 45 Cycles accessLatency; 46 unsigned int bankBits; --- 32 unchanged lines hidden --- | 39#include "sim/core.hh" 40 41class BankedArray 42{ 43 private: 44 unsigned int banks; 45 Cycles accessLatency; 46 unsigned int bankBits; --- 32 unchanged lines hidden --- |