BankedArray.hh (10917:c38f28fad4c3) BankedArray.hh (10919:80069a602c83)
1/*
2 * Copyright (c) 2012 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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30 */
31
32#ifndef __MEM_RUBY_STRUCTURES_BANKEDARRAY_HH__
33#define __MEM_RUBY_STRUCTURES_BANKEDARRAY_HH__
34
35#include <vector>
36
37#include "mem/ruby/common/TypeDefines.hh"
1/*
2 * Copyright (c) 2012 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 21 unchanged lines hidden (view full) ---

30 */
31
32#ifndef __MEM_RUBY_STRUCTURES_BANKEDARRAY_HH__
33#define __MEM_RUBY_STRUCTURES_BANKEDARRAY_HH__
34
35#include <vector>
36
37#include "mem/ruby/common/TypeDefines.hh"
38#include "mem/ruby/system/System.hh"
38#include "sim/core.hh"
39
40class BankedArray
41{
42 private:
43 unsigned int banks;
44 Cycles accessLatency;
45 unsigned int bankBits;
46 unsigned int startIndexBit;
39#include "sim/core.hh"
40
41class BankedArray
42{
43 private:
44 unsigned int banks;
45 Cycles accessLatency;
46 unsigned int bankBits;
47 unsigned int startIndexBit;
48 RubySystem *m_ruby_system;
47
48 class AccessRecord
49 {
50 public:
51 AccessRecord() : idx(0), startAccess(0), endAccess(0) {}
52 int64 idx;
53 Tick startAccess;
54 Tick endAccess;
55 };
56
57 // If the tick event is scheduled then the bank is busy
58 // otherwise, schedule the event and wait for it to complete
59 std::vector<AccessRecord> busyBanks;
60
61 unsigned int mapIndexToBank(int64 idx);
62
63 public:
64 BankedArray(unsigned int banks, Cycles accessLatency,
49
50 class AccessRecord
51 {
52 public:
53 AccessRecord() : idx(0), startAccess(0), endAccess(0) {}
54 int64 idx;
55 Tick startAccess;
56 Tick endAccess;
57 };
58
59 // If the tick event is scheduled then the bank is busy
60 // otherwise, schedule the event and wait for it to complete
61 std::vector<AccessRecord> busyBanks;
62
63 unsigned int mapIndexToBank(int64 idx);
64
65 public:
66 BankedArray(unsigned int banks, Cycles accessLatency,
65 unsigned int startIndexBit);
67 unsigned int startIndexBit, RubySystem *rs);
66
67 // Note: We try the access based on the cache index, not the address
68 // This is so we don't get aliasing on blocks being replaced
69 bool tryAccess(int64 idx);
70
71};
72
73#endif
68
69 // Note: We try the access based on the cache index, not the address
70 // This is so we don't get aliasing on blocks being replaced
71 bool tryAccess(int64 idx);
72
73};
74
75#endif