1/* 2 * Copyright (c) 2012 Advanced Micro Devices, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 35 unchanged lines hidden (view full) --- 44 Cycles accessLatency; 45 unsigned int bankBits; 46 unsigned int startIndexBit; 47 48 class AccessRecord 49 { 50 public: 51 AccessRecord() : idx(0), startAccess(0), endAccess(0) {} |
52 int64 idx; |
53 Tick startAccess; 54 Tick endAccess; 55 }; 56 57 // If the tick event is scheduled then the bank is busy 58 // otherwise, schedule the event and wait for it to complete 59 std::vector<AccessRecord> busyBanks; 60 |
61 unsigned int mapIndexToBank(int64 idx); |
62 63 public: 64 BankedArray(unsigned int banks, Cycles accessLatency, unsigned int startIndexBit); 65 66 // Note: We try the access based on the cache index, not the address 67 // This is so we don't get aliasing on blocks being replaced |
68 bool tryAccess(int64 idx); |
69 70}; 71 72#endif |