1/*
2 * Copyright (c) 2012 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Author: Brad Beckmann
29 *
30 */
31
| 1/*
2 * Copyright (c) 2012 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Author: Brad Beckmann
29 *
30 */
31
|
34
35#include <vector>
36
37#include "mem/ruby/common/TypeDefines.hh"
38#include "sim/core.hh"
39
40class BankedArray
41{
42 private:
43 unsigned int banks;
44 Cycles accessLatency;
45 unsigned int bankBits;
46 unsigned int startIndexBit;
47
48 class AccessRecord
49 {
50 public:
51 AccessRecord() : idx(0), startAccess(0), endAccess(0) {}
52 int64 idx;
53 Tick startAccess;
54 Tick endAccess;
55 };
56
57 // If the tick event is scheduled then the bank is busy
58 // otherwise, schedule the event and wait for it to complete
59 std::vector<AccessRecord> busyBanks;
60
61 unsigned int mapIndexToBank(int64 idx);
62
63 public:
64 BankedArray(unsigned int banks, Cycles accessLatency, unsigned int startIndexBit);
65
66 // Note: We try the access based on the cache index, not the address
67 // This is so we don't get aliasing on blocks being replaced
68 bool tryAccess(int64 idx);
69
70};
71
72#endif
| 34
35#include <vector>
36
37#include "mem/ruby/common/TypeDefines.hh"
38#include "sim/core.hh"
39
40class BankedArray
41{
42 private:
43 unsigned int banks;
44 Cycles accessLatency;
45 unsigned int bankBits;
46 unsigned int startIndexBit;
47
48 class AccessRecord
49 {
50 public:
51 AccessRecord() : idx(0), startAccess(0), endAccess(0) {}
52 int64 idx;
53 Tick startAccess;
54 Tick endAccess;
55 };
56
57 // If the tick event is scheduled then the bank is busy
58 // otherwise, schedule the event and wait for it to complete
59 std::vector<AccessRecord> busyBanks;
60
61 unsigned int mapIndexToBank(int64 idx);
62
63 public:
64 BankedArray(unsigned int banks, Cycles accessLatency, unsigned int startIndexBit);
65
66 // Note: We try the access based on the cache index, not the address
67 // This is so we don't get aliasing on blocks being replaced
68 bool tryAccess(int64 idx);
69
70};
71
72#endif
|