BankedArray.hh (11031:3815437cb231) | BankedArray.hh (11049:dfb0aa3f0649) |
---|---|
1/* 2 * Copyright (c) 2012 Advanced Micro Devices, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 37 unchanged lines hidden (view full) --- 46 unsigned int bankBits; 47 unsigned int startIndexBit; 48 RubySystem *m_ruby_system; 49 50 class AccessRecord 51 { 52 public: 53 AccessRecord() : idx(0), startAccess(0), endAccess(0) {} | 1/* 2 * Copyright (c) 2012 Advanced Micro Devices, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 37 unchanged lines hidden (view full) --- 46 unsigned int bankBits; 47 unsigned int startIndexBit; 48 RubySystem *m_ruby_system; 49 50 class AccessRecord 51 { 52 public: 53 AccessRecord() : idx(0), startAccess(0), endAccess(0) {} |
54 int64_t idx; | 54 int64 idx; |
55 Tick startAccess; 56 Tick endAccess; 57 }; 58 59 // If the tick event is scheduled then the bank is busy 60 // otherwise, schedule the event and wait for it to complete 61 std::vector<AccessRecord> busyBanks; 62 | 55 Tick startAccess; 56 Tick endAccess; 57 }; 58 59 // If the tick event is scheduled then the bank is busy 60 // otherwise, schedule the event and wait for it to complete 61 std::vector<AccessRecord> busyBanks; 62 |
63 unsigned int mapIndexToBank(int64_t idx); | 63 unsigned int mapIndexToBank(int64 idx); |
64 65 public: 66 BankedArray(unsigned int banks, Cycles accessLatency, 67 unsigned int startIndexBit, RubySystem *rs); 68 69 // Note: We try the access based on the cache index, not the address 70 // This is so we don't get aliasing on blocks being replaced | 64 65 public: 66 BankedArray(unsigned int banks, Cycles accessLatency, 67 unsigned int startIndexBit, RubySystem *rs); 68 69 // Note: We try the access based on the cache index, not the address 70 // This is so we don't get aliasing on blocks being replaced |
71 bool tryAccess(int64_t idx); | 71 bool tryAccess(int64 idx); |
72 | 72 |
73 void reserve(int64_t idx); | 73 void reserve(int64 idx); |
74 75 Cycles getLatency() const { return accessLatency; } 76}; 77 78#endif | 74 75 Cycles getLatency() const { return accessLatency; } 76}; 77 78#endif |