BankedArray.cc (10314:94b6b28fc968) BankedArray.cc (10919:80069a602c83)
1/*
2 * Copyright (c) 2012 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 20 unchanged lines hidden (view full) ---

29 *
30 */
31
32#include "base/intmath.hh"
33#include "mem/ruby/structures/BankedArray.hh"
34#include "mem/ruby/system/System.hh"
35
36BankedArray::BankedArray(unsigned int banks, Cycles accessLatency,
1/*
2 * Copyright (c) 2012 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 20 unchanged lines hidden (view full) ---

29 *
30 */
31
32#include "base/intmath.hh"
33#include "mem/ruby/structures/BankedArray.hh"
34#include "mem/ruby/system/System.hh"
35
36BankedArray::BankedArray(unsigned int banks, Cycles accessLatency,
37 unsigned int startIndexBit)
37 unsigned int startIndexBit, RubySystem *rs)
38 : m_ruby_system(rs)
38{
39 this->banks = banks;
40 this->accessLatency = accessLatency;
41 this->startIndexBit = startIndexBit;
42
43 if (banks != 0) {
44 bankBits = floorLog2(banks);
45 }

--- 19 unchanged lines hidden (view full) ---

65 // in the same cycle for the same addr
66 return true;
67 }
68 }
69
70 busyBanks[bank].idx = idx;
71 busyBanks[bank].startAccess = curTick();
72 busyBanks[bank].endAccess = curTick() +
39{
40 this->banks = banks;
41 this->accessLatency = accessLatency;
42 this->startIndexBit = startIndexBit;
43
44 if (banks != 0) {
45 bankBits = floorLog2(banks);
46 }

--- 19 unchanged lines hidden (view full) ---

66 // in the same cycle for the same addr
67 return true;
68 }
69 }
70
71 busyBanks[bank].idx = idx;
72 busyBanks[bank].startAccess = curTick();
73 busyBanks[bank].endAccess = curTick() +
73 (accessLatency-1) * g_system_ptr->clockPeriod();
74 (accessLatency-1) * m_ruby_system->clockPeriod();
74
75 return true;
76}
77
78unsigned int
79BankedArray::mapIndexToBank(int64 idx)
80{
81 if (banks == 1) {
82 return 0;
83 }
84 return idx % banks;
85}
75
76 return true;
77}
78
79unsigned int
80BankedArray::mapIndexToBank(int64 idx)
81{
82 if (banks == 1) {
83 return 0;
84 }
85 return idx % banks;
86}