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> #include "mem/ruby/system/DirectoryMemory.hh"
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> /*
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<
< #ifdef MACHINETYPE_Collector
< #define MACHINETYPE_COLLECTOR_ENUM MachineType_Collector
< #else
< #define MACHINETYPE_COLLECTOR_ENUM MachineType_NUM
< #endif
<
<
< // used to determine the correct L1 set
< // input parameters are the address and number of set bits for the L1 cache
< // returns a value between 0 and the total number of L1 cache sets
< inline
< int map_address_to_L1CacheSet(const Address& addr, int cache_num_set_bits)
---
> */
> /*
> inline MachineID map_Address_to_L2Cache(const Address & addr)
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< return addr.bitSelect(RubyConfig::dataBlockBits(),
< RubyConfig::dataBlockBits()+cache_num_set_bits-1);
---
> int L2bank = 0;
> MachineID mach = {MACHINETYPE_L2CACHE_ENUM, 0};
> L2bank = addr.bitSelect(RubySystem::getBlockSizeBits(),
> RubySystem::getBlockSizeBits() + RubyConfig::getNumberOfCachesPerLevel(2)-1);
> mach.num = L2bank;
> return mach;
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< // used to determine the correct L2 set
< // input parameters are the address and number of set bits for the L2 cache
< // returns a value between 0 and the total number of L2 cache sets
< inline
< int map_address_to_L2CacheSet(const Address& addr, int cache_num_set_bits)
< {
< assert(cache_num_set_bits == L2_CACHE_NUM_SETS_BITS); // ensure the l2 bank mapping functions agree with l2 set bits
<
< if (MAP_L2BANKS_TO_LOWEST_BITS) {
< return addr.bitSelect(RubyConfig::dataBlockBits()+RubyConfig::L2CachePerChipBits(),
< RubyConfig::dataBlockBits()+RubyConfig::L2CachePerChipBits()+cache_num_set_bits-1);
< } else {
< return addr.bitSelect(RubyConfig::dataBlockBits(),
< RubyConfig::dataBlockBits()+cache_num_set_bits-1);
< }
< }
<
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> return map_Address_to_L2Cache(addr);
>
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< if (MAP_L2BANKS_TO_LOWEST_BITS) {
< L2bank = addr.bitSelect(RubyConfig::dataBlockBits(),
< RubyConfig::dataBlockBits()+RubyConfig::L2CachePerChipBits()-1);
---
> if (RubyConfig::getMAP_L2BANKS_TO_LOWEST_BITS()) {
> L2bank = addr.bitSelect(RubySystem::getBlockSizeBits(),
> RubySystem::getBlockSizeBits()+RubyConfig::L2CachePerChipBits()-1);
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< L2bank = addr.bitSelect(RubyConfig::dataBlockBits()+L2_CACHE_NUM_SETS_BITS,
< RubyConfig::dataBlockBits()+L2_CACHE_NUM_SETS_BITS+RubyConfig::L2CachePerChipBits()-1);
---
> L2bank = addr.bitSelect(RubySystem::getBlockSizeBits()+RubyConfig::getL2_CACHE_NUM_SETS_BITS(),
> RubySystem::getBlockSizeBits()+RubyConfig::getL2_CACHE_NUM_SETS_BITS()+RubyConfig::L2CachePerChipBits()-1);
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>
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>
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>
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> return map_Address_to_L2Cache(addr);
>
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> L2bank = addr.bitSelect(RubySystem::getBlockSizeBits(),
> RubySystem::getBlockSizeBits() + RubyConfig::numberOfCachesPerLevel(2)-1);
> mach.num = L2bank;
> return mach
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< if (RubyConfig::L2CachePerChipBits() > 0) {
< if (MAP_L2BANKS_TO_LOWEST_BITS) {
< L2bank = addr.bitSelect(RubyConfig::dataBlockBits(),
< RubyConfig::dataBlockBits()+RubyConfig::L2CachePerChipBits()-1);
< } else {
< L2bank = addr.bitSelect(RubyConfig::dataBlockBits()+L2_CACHE_NUM_SETS_BITS,
< RubyConfig::dataBlockBits()+L2_CACHE_NUM_SETS_BITS+RubyConfig::L2CachePerChipBits()-1);
< }
< }
<
< assert(L2bank < RubyConfig::numberOfL2CachePerChip());
< assert(L2bank >= 0);
<
< mach.num = L2ChipId*RubyConfig::numberOfL2CachePerChip() // base #
< + L2bank; // bank #
< assert(mach.num < RubyConfig::numberOfL2Cache());
< return mach;
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> */
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>
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< NodeID dirNode = 0;
<
< if (RubyConfig::memoryBits() > 0) {
< dirNode = addr.bitSelect(RubyConfig::dataBlockBits(),
< RubyConfig::dataBlockBits()+RubyConfig::memoryBits()-1);
< }
<
< // Index indexHighPortion = address.bitSelect(MEMORY_SIZE_BITS-1, PAGE_SIZE_BITS+NUMBER_OF_MEMORY_MODULE_BITS);
< // Index indexLowPortion = address.bitSelect(DATA_BLOCK_BITS, PAGE_SIZE_BITS-1);
<
< //Index index = indexLowPortion | (indexHighPortion << (PAGE_SIZE_BITS - DATA_BLOCK_BITS));
<
< /*
<
< ADDRESS_WIDTH MEMORY_SIZE_BITS PAGE_SIZE_BITS DATA_BLOCK_BITS
< | | | |
< \ / \ / \ / \ / 0
< -----------------------------------------------------------------------
< | unused |xxxxxxxxxxxxxxx| |xxxxxxxxxxxxxxx| |
< | |xxxxxxxxxxxxxxx| |xxxxxxxxxxxxxxx| |
< -----------------------------------------------------------------------
< indexHighPortion indexLowPortion
< <------->
< NUMBER_OF_MEMORY_MODULE_BITS
< */
<
< assert(dirNode < RubyConfig::numberOfMemories());
< assert(dirNode >= 0);
< return dirNode;
---
> return DirectoryMemory::mapAddressToDirectoryVersion(addr);
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< MachineID map_Address_to_CentralArbiterNode(const Address& addr)
---
> MachineID map_Address_to_DMA(const Address & addr)
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< MachineType t = MACHINETYPE_PERSISTENTARBITER_ENUM;
< MachineID mach = {t, map_Address_to_DirectoryNode(addr)};
<
< assert(mach.num < RubyConfig::numberOfMemories());
< assert(mach.num >= 0);
< return mach;
---
> MachineID dma = {MachineType_DMA, 0};
> return dma;
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> /*
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< NetDest getMultiStaticL2BankNetDest(const Address& addr, const Set& sharers) // set of L2RubyNodes
< {
< NetDest dest;
<
< for (int i = 0; i < sharers.getSize(); i++) {
< if (sharers.isElement(i)) {
< dest.add(map_L2ChipId_to_L2Cache(addr,i));
< }
< }
< return dest;
< }
<
< inline
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> */
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< inline
< NetDest getLocalL1IDs(MachineID mach)
< {
< assert(MACHINETYPE_L1CACHE_ENUM != MachineType_NUM);
<
< NetDest ret;
<
< if (mach.type == MACHINETYPE_L1CACHE_ENUM) {
<
< int start = (mach.num / RubyConfig::numberOfL1CachePerChip()) * RubyConfig::numberOfProcsPerChip();
<
< for (int i = start; i < (start + RubyConfig::numberOfProcsPerChip()); i++) {
< MachineID mach = { MACHINETYPE_L1CACHE_ENUM, i };
< ret.add( mach );
< }
< }
< else if (mach.type == MACHINETYPE_L2CACHE_ENUM) {
<
< int chip = mach.num/RubyConfig::numberOfL2CachePerChip();
< int start = ( chip*RubyConfig::numberOfL1CachePerChip());
< for (int i = start; i < (start + RubyConfig::numberOfL1CachePerChip()); i++) {
< MachineID mach = { MACHINETYPE_L1CACHE_ENUM, i };
< ret.add( mach );
< }
< }
<
< return ret;
< }
<
< inline
< NetDest getExternalL1IDs(MachineID L1)
< {
< NetDest ret;
<
< assert(MACHINETYPE_L1CACHE_ENUM != MachineType_NUM);
<
< for (int i = 0; i < RubyConfig::numberOfProcessors(); i++) {
< // ret.add( (NodeID) i);
< MachineID mach = { MACHINETYPE_L1CACHE_ENUM, i };
< ret.add( mach );
< }
<
< ret.removeNetDest(getLocalL1IDs(L1));
<
< return ret;
< }
<
< inline
< bool isLocalProcessor(MachineID thisId, MachineID tarID)
< {
< int start = (thisId.num / RubyConfig::numberOfProcsPerChip()) * RubyConfig::numberOfProcsPerChip();
<
< for (int i = start; i < (start + RubyConfig::numberOfProcsPerChip()); i++) {
< if (i == tarID.num) {
< return true;
< }
< }
< return false;
< }
<
<
< inline
< NetDest getAllPertinentL2Banks(const Address& addr) // set of L2RubyNodes
< {
< NetDest dest;
<
< for (int i = 0; i < RubyConfig::numberOfChips(); i++) {
< dest.add(map_L2ChipId_to_L2Cache(addr,i));
< }
< return dest;
< }
<
< inline
< bool isL1OnChip(MachineID L1machID, NodeID L2NodeID)
< {
< if (L1machID.type == MACHINETYPE_L1CACHE_ENUM) {
< return (L1machID.num == L2NodeID);
< } else {
< return false;
< }
< }
<
< inline
< bool isL2OnChip(MachineID L2machID, NodeID L2NodeID)
< {
< if (L2machID.type == MACHINETYPE_L2CACHE_ENUM) {
< return (L2machID.num == L2NodeID);
< } else {
< return false;
< }
< }
<
< inline
< NodeID closest_clockwise_distance(NodeID this_node, NodeID next_node)
< {
< if (this_node <= next_node) {
< return (next_node - this_node);
< } else {
< return (next_node - this_node + RubyConfig::numberOfChips());
< }
< }
<
< inline
< bool closer_clockwise_processor(NodeID this_node, NodeID newer, NodeID older)
< {
< return (closest_clockwise_distance(this_node, newer) < closest_clockwise_distance(this_node, older));
< }
<
< extern inline NodeID getChipID(MachineID L2machID)
< {
< return (L2machID.num%RubyConfig::numberOfChips())/RubyConfig::numberOfProcsPerChip();
< }
<
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< extern inline NodeID machineIDToVersion(MachineID machID)
< {
< return machID.num/RubyConfig::numberOfChips();
< }
<
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<
---
> /*
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< return machID.num/RubyConfig::numberOfL2CachePerChip();
---
> int L2bank = machID.num;
> int banks_seen = 0;
> for (int i=0;i<RubyConfig::getNumberOfChips();i++) {
> for (int j=0;j<RubyConfig::getNumberOfCachesPerLevelPerChip(2,i);j++) {
> if (banks_seen == L2bank)
> return i;
> banks_seen++;
> }
> }
> assert(0);
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<
< extern inline MachineID getCollectorDest(MachineID L1MachID)
< {
< MachineID mach = {MACHINETYPE_COLLECTOR_ENUM, L1MachID.num};
< return mach;
< }
<
< extern inline MachineID getCollectorL1Cache(MachineID colID)
< {
< MachineID mach = {MACHINETYPE_L1CACHE_ENUM, colID.num};
< return mach;
< }
<
---
> */
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< } else if (machType == MACHINETYPE_COLLECTOR_ENUM) {
< return GenericMachineType_Collector;