1#include <iostream>
2
3#include "mem/ruby/slicc_interface/RubyRequest.hh"
4
5using namespace std;
6
7void
8RubyRequest::print(ostream& out) const

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34{
35 // This needs a little explanation. I am not sure if this message
36 // should be written. Essentially the question is how are writes
37 // ordered. I am assuming that if a functional write is issued after
38 // a timing write to the same address, then the functional write
39 // has to overwrite the data for the timing request, even if the
40 // timing request has still not been ordered globally.
41
42 Address pktLineAddr(pkt->getAddr());
43 pktLineAddr.makeLineAddress();
44
45 if (pktLineAddr == m_LineAddress) {
46 uint8_t *pktData = pkt->getPtr<uint8_t>(true);
47 unsigned int size_in_bytes = pkt->getSize();
48 unsigned startByte = pkt->getAddr() - m_LineAddress.getAddress();
49
50 for (unsigned i = 0; i < size_in_bytes; ++i) {
51 data[i + startByte] = pktData[i];
52 }
53
54 return true;
55 }
56 return false;
57}