Controller.py (10524:fff17530cef6) Controller.py (12065:e3e51756dfef)
1# Copyright (c) 2017 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
1# Copyright (c) 2009 Advanced Micro Devices, Inc.
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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32from MemObject import MemObject
33
34class RubyController(MemObject):
35 type = 'RubyController'
36 cxx_class = 'AbstractController'
37 cxx_header = "mem/ruby/slicc_interface/AbstractController.hh"
38 abstract = True
39 version = Param.Int("")
13# Copyright (c) 2009 Advanced Micro Devices, Inc.
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright

--- 23 unchanged lines hidden (view full) ---

44from MemObject import MemObject
45
46class RubyController(MemObject):
47 type = 'RubyController'
48 cxx_class = 'AbstractController'
49 cxx_header = "mem/ruby/slicc_interface/AbstractController.hh"
50 abstract = True
51 version = Param.Int("")
52 addr_ranges = VectorParam.AddrRange([AllMemory], "Address range this "
53 "controller responds to")
40 cluster_id = Param.UInt32(0, "Id of this controller's cluster")
41
42 transitions_per_cycle = \
43 Param.Int(32, "no. of SLICC state machine transitions per cycle")
44 buffer_size = Param.UInt32(0, "max buffer size 0 means infinite")
45
46 recycle_latency = Param.Cycles(10, "")
47 number_of_TBEs = Param.Int(256, "")
48 ruby_system = Param.RubySystem("")
49
50 memory = MasterPort("Port for attaching a memory controller")
51 system = Param.System(Parent.any, "system object parameter")
54 cluster_id = Param.UInt32(0, "Id of this controller's cluster")
55
56 transitions_per_cycle = \
57 Param.Int(32, "no. of SLICC state machine transitions per cycle")
58 buffer_size = Param.UInt32(0, "max buffer size 0 means infinite")
59
60 recycle_latency = Param.Cycles(10, "")
61 number_of_TBEs = Param.Int(256, "")
62 ruby_system = Param.RubySystem("")
63
64 memory = MasterPort("Port for attaching a memory controller")
65 system = Param.System(Parent.any, "system object parameter")