Controller.py (10096:e0167dda38dc) | Controller.py (10524:fff17530cef6) |
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1# Copyright (c) 2009 Advanced Micro Devices, Inc. 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 14 unchanged lines hidden (view full) --- 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Steve Reinhardt 28# Brad Beckmann 29 30from m5.params import * | 1# Copyright (c) 2009 Advanced Micro Devices, Inc. 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 14 unchanged lines hidden (view full) --- 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Steve Reinhardt 28# Brad Beckmann 29 30from m5.params import * |
31from ClockedObject import ClockedObject | 31from m5.proxy import * 32from MemObject import MemObject |
32 | 33 |
33class RubyController(ClockedObject): | 34class RubyController(MemObject): |
34 type = 'RubyController' 35 cxx_class = 'AbstractController' 36 cxx_header = "mem/ruby/slicc_interface/AbstractController.hh" 37 abstract = True 38 version = Param.Int("") 39 cluster_id = Param.UInt32(0, "Id of this controller's cluster") 40 41 transitions_per_cycle = \ 42 Param.Int(32, "no. of SLICC state machine transitions per cycle") 43 buffer_size = Param.UInt32(0, "max buffer size 0 means infinite") 44 45 recycle_latency = Param.Cycles(10, "") 46 number_of_TBEs = Param.Int(256, "") 47 ruby_system = Param.RubySystem("") 48 | 35 type = 'RubyController' 36 cxx_class = 'AbstractController' 37 cxx_header = "mem/ruby/slicc_interface/AbstractController.hh" 38 abstract = True 39 version = Param.Int("") 40 cluster_id = Param.UInt32(0, "Id of this controller's cluster") 41 42 transitions_per_cycle = \ 43 Param.Int(32, "no. of SLICC state machine transitions per cycle") 44 buffer_size = Param.UInt32(0, "max buffer size 0 means infinite") 45 46 recycle_latency = Param.Cycles(10, "") 47 number_of_TBEs = Param.Int(256, "") 48 ruby_system = Param.RubySystem("") 49 |
49 peer = Param.RubyController(NULL, "") | 50 memory = MasterPort("Port for attaching a memory controller") 51 system = Param.System(Parent.any, "system object parameter") |