AbstractController.cc (12680:91f4d6668b4f) AbstractController.cc (12749:223c83ed9979)
1/*
2 * Copyright (c) 2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 226 unchanged lines hidden (view full) ---

235{
236 return memoryPort;
237}
238
239void
240AbstractController::queueMemoryRead(const MachineID &id, Addr addr,
241 Cycles latency)
242{
1/*
2 * Copyright (c) 2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 226 unchanged lines hidden (view full) ---

235{
236 return memoryPort;
237}
238
239void
240AbstractController::queueMemoryRead(const MachineID &id, Addr addr,
241 Cycles latency)
242{
243 RequestPtr req = new Request(addr, RubySystem::getBlockSizeBytes(), 0,
244 m_masterId);
243 RequestPtr req = std::make_shared<Request>(
244 addr, RubySystem::getBlockSizeBytes(), 0, m_masterId);
245
246 PacketPtr pkt = Packet::createRead(req);
247 uint8_t *newData = new uint8_t[RubySystem::getBlockSizeBytes()];
248 pkt->dataDynamic(newData);
249
250 SenderState *s = new SenderState(id);
251 pkt->pushSenderState(s);
252

--- 6 unchanged lines hidden (view full) ---

259
260 memoryPort.schedTimingReq(pkt, clockEdge(latency));
261}
262
263void
264AbstractController::queueMemoryWrite(const MachineID &id, Addr addr,
265 Cycles latency, const DataBlock &block)
266{
245
246 PacketPtr pkt = Packet::createRead(req);
247 uint8_t *newData = new uint8_t[RubySystem::getBlockSizeBytes()];
248 pkt->dataDynamic(newData);
249
250 SenderState *s = new SenderState(id);
251 pkt->pushSenderState(s);
252

--- 6 unchanged lines hidden (view full) ---

259
260 memoryPort.schedTimingReq(pkt, clockEdge(latency));
261}
262
263void
264AbstractController::queueMemoryWrite(const MachineID &id, Addr addr,
265 Cycles latency, const DataBlock &block)
266{
267 RequestPtr req = new Request(addr, RubySystem::getBlockSizeBytes(), 0,
268 m_masterId);
267 RequestPtr req = std::make_shared<Request>(
268 addr, RubySystem::getBlockSizeBytes(), 0, m_masterId);
269
270 PacketPtr pkt = Packet::createWrite(req);
271 uint8_t *newData = new uint8_t[RubySystem::getBlockSizeBytes()];
272 pkt->dataDynamic(newData);
273 memcpy(newData, block.getData(0, RubySystem::getBlockSizeBytes()),
274 RubySystem::getBlockSizeBytes());
275
276 SenderState *s = new SenderState(id);

--- 10 unchanged lines hidden (view full) ---

287 memoryPort.schedTimingReq(pkt, clockEdge(latency));
288}
289
290void
291AbstractController::queueMemoryWritePartial(const MachineID &id, Addr addr,
292 Cycles latency,
293 const DataBlock &block, int size)
294{
269
270 PacketPtr pkt = Packet::createWrite(req);
271 uint8_t *newData = new uint8_t[RubySystem::getBlockSizeBytes()];
272 pkt->dataDynamic(newData);
273 memcpy(newData, block.getData(0, RubySystem::getBlockSizeBytes()),
274 RubySystem::getBlockSizeBytes());
275
276 SenderState *s = new SenderState(id);

--- 10 unchanged lines hidden (view full) ---

287 memoryPort.schedTimingReq(pkt, clockEdge(latency));
288}
289
290void
291AbstractController::queueMemoryWritePartial(const MachineID &id, Addr addr,
292 Cycles latency,
293 const DataBlock &block, int size)
294{
295 RequestPtr req = new Request(addr, size, 0, m_masterId);
295 RequestPtr req = std::make_shared<Request>(addr, size, 0, m_masterId);
296
297 PacketPtr pkt = Packet::createWrite(req);
298 uint8_t *newData = new uint8_t[size];
299 pkt->dataDynamic(newData);
300 memcpy(newData, block.getData(getOffset(addr), size), size);
301
302 SenderState *s = new SenderState(id);
303 pkt->pushSenderState(s);

--- 47 unchanged lines hidden (view full) ---

351 } else if (pkt->isWrite()) {
352 (*msg).m_Type = MemoryRequestType_MEMORY_WB;
353 (*msg).m_MessageSize = MessageSizeType_Writeback_Control;
354 } else {
355 panic("Incorrect packet type received from memory controller!");
356 }
357
358 getMemoryQueue()->enqueue(msg, clockEdge(), cyclesToTicks(Cycles(1)));
296
297 PacketPtr pkt = Packet::createWrite(req);
298 uint8_t *newData = new uint8_t[size];
299 pkt->dataDynamic(newData);
300 memcpy(newData, block.getData(getOffset(addr), size), size);
301
302 SenderState *s = new SenderState(id);
303 pkt->pushSenderState(s);

--- 47 unchanged lines hidden (view full) ---

351 } else if (pkt->isWrite()) {
352 (*msg).m_Type = MemoryRequestType_MEMORY_WB;
353 (*msg).m_MessageSize = MessageSizeType_Writeback_Control;
354 } else {
355 panic("Incorrect packet type received from memory controller!");
356 }
357
358 getMemoryQueue()->enqueue(msg, clockEdge(), cyclesToTicks(Cycles(1)));
359 delete pkt->req;
360 delete pkt;
361}
362
363Tick
364AbstractController::recvAtomic(PacketPtr pkt)
365{
366 return ticksToCycles(memoryPort.sendAtomic(pkt));
367}

--- 25 unchanged lines hidden --- 		359 delete pkt;
360}
361
362Tick
363AbstractController::recvAtomic(PacketPtr pkt)
364{
365 return ticksToCycles(memoryPort.sendAtomic(pkt));
366}

--- 25 unchanged lines hidden ---