AbstractController.cc (10311:ad9c042dce54) | AbstractController.cc (10524:fff17530cef6) |
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1/* | 1/* |
2 * Copyright (c) 2011 Mark D. Hill and David A. Wood | 2 * Copyright (c) 2011-2014 Mark D. Hill and David A. Wood |
3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the --- 10 unchanged lines hidden (view full) --- 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 | 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the --- 10 unchanged lines hidden (view full) --- 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 |
29#include "mem/protocol/MemoryMsg.hh" |
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29#include "mem/ruby/slicc_interface/AbstractController.hh" 30#include "mem/ruby/system/Sequencer.hh" 31#include "mem/ruby/system/System.hh" | 30#include "mem/ruby/slicc_interface/AbstractController.hh" 31#include "mem/ruby/system/Sequencer.hh" 32#include "mem/ruby/system/System.hh" |
33#include "sim/system.hh" |
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32 33AbstractController::AbstractController(const Params *p) | 34 35AbstractController::AbstractController(const Params *p) |
34 : ClockedObject(p), Consumer(this) | 36 : MemObject(p), Consumer(this), m_version(p->version), 37 m_clusterID(p->cluster_id), 38 m_masterId(p->system->getMasterId(name())), m_is_blocking(false), 39 m_number_of_TBEs(p->number_of_TBEs), 40 m_transitions_per_cycle(p->transitions_per_cycle), 41 m_buffer_size(p->buffer_size), m_recycle_latency(p->recycle_latency), 42 memoryPort(csprintf("%s.memory", name()), this, ""), 43 m_responseFromMemory_ptr(new MessageBuffer()) |
35{ | 44{ |
36 m_version = p->version; 37 m_clusterID = p->cluster_id; | 45 // Set the sender pointer of the response message buffer from the 46 // memory controller. 47 // This pointer is used for querying for the current time. 48 m_responseFromMemory_ptr->setSender(this); 49 m_responseFromMemory_ptr->setReceiver(this); 50 m_responseFromMemory_ptr->setOrdering(false); |
38 | 51 |
39 m_transitions_per_cycle = p->transitions_per_cycle; 40 m_buffer_size = p->buffer_size; 41 m_recycle_latency = p->recycle_latency; 42 m_number_of_TBEs = p->number_of_TBEs; 43 m_is_blocking = false; 44 | |
45 if (m_version == 0) { 46 // Combine the statistics from all controllers 47 // of this particular type. 48 Stats::registerDumpCallback(new StatsCallback(this)); 49 } 50} 51 52void --- 129 unchanged lines hidden (view full) --- 182void 183AbstractController::unblock(Address addr) 184{ 185 m_block_map.erase(addr); 186 if (m_block_map.size() == 0) { 187 m_is_blocking = false; 188 } 189} | 52 if (m_version == 0) { 53 // Combine the statistics from all controllers 54 // of this particular type. 55 Stats::registerDumpCallback(new StatsCallback(this)); 56 } 57} 58 59void --- 129 unchanged lines hidden (view full) --- 189void 190AbstractController::unblock(Address addr) 191{ 192 m_block_map.erase(addr); 193 if (m_block_map.size() == 0) { 194 m_is_blocking = false; 195 } 196} |
197 198BaseMasterPort & 199AbstractController::getMasterPort(const std::string &if_name, 200 PortID idx) 201{ 202 return memoryPort; 203} 204 205void 206AbstractController::queueMemoryRead(const MachineID &id, Address addr, 207 Cycles latency) 208{ 209 RequestPtr req = new Request(addr.getAddress(), 210 RubySystem::getBlockSizeBytes(), 0, 211 m_masterId); 212 213 PacketPtr pkt = Packet::createRead(req); 214 uint8_t *newData = new uint8_t[RubySystem::getBlockSizeBytes()]; 215 pkt->dataDynamic(newData); 216 217 SenderState *s = new SenderState(id); 218 pkt->pushSenderState(s); 219 220 memoryPort.schedTimingReq(pkt, clockEdge(latency)); 221} 222 223void 224AbstractController::queueMemoryWrite(const MachineID &id, Address addr, 225 Cycles latency, const DataBlock &block) 226{ 227 RequestPtr req = new Request(addr.getAddress(), 228 RubySystem::getBlockSizeBytes(), 0, 229 m_masterId); 230 231 PacketPtr pkt = Packet::createWrite(req); 232 uint8_t *newData = new uint8_t[RubySystem::getBlockSizeBytes()]; 233 pkt->dataDynamic(newData); 234 memcpy(newData, block.getData(0, RubySystem::getBlockSizeBytes()), 235 RubySystem::getBlockSizeBytes()); 236 237 SenderState *s = new SenderState(id); 238 pkt->pushSenderState(s); 239 240 // Create a block and copy data from the block. 241 memoryPort.schedTimingReq(pkt, clockEdge(latency)); 242} 243 244void 245AbstractController::queueMemoryWritePartial(const MachineID &id, Address addr, 246 Cycles latency, 247 const DataBlock &block, int size) 248{ 249 RequestPtr req = new Request(addr.getAddress(), 250 RubySystem::getBlockSizeBytes(), 0, 251 m_masterId); 252 253 PacketPtr pkt = Packet::createWrite(req); 254 uint8_t *newData = new uint8_t[size]; 255 pkt->dataDynamic(newData); 256 memcpy(newData, block.getData(addr.getOffset(), size), size); 257 258 SenderState *s = new SenderState(id); 259 pkt->pushSenderState(s); 260 261 // Create a block and copy data from the block. 262 memoryPort.schedTimingReq(pkt, clockEdge(latency)); 263} 264 265void 266AbstractController::functionalMemoryRead(PacketPtr pkt) 267{ 268 memoryPort.sendFunctional(pkt); 269} 270 271int 272AbstractController::functionalMemoryWrite(PacketPtr pkt) 273{ 274 int num_functional_writes = 0; 275 276 // Check the message buffer that runs from the memory to the controller. 277 num_functional_writes += m_responseFromMemory_ptr->functionalWrite(pkt); 278 279 // Check the buffer from the controller to the memory. 280 if (memoryPort.checkFunctional(pkt)) { 281 num_functional_writes++; 282 } 283 284 // Update memory itself. 285 memoryPort.sendFunctional(pkt); 286 return num_functional_writes + 1; 287} 288 289void 290AbstractController::recvTimingResp(PacketPtr pkt) 291{ 292 assert(pkt->isResponse()); 293 294 std::shared_ptr<MemoryMsg> msg = std::make_shared<MemoryMsg>(clockEdge()); 295 (*msg).m_Addr.setAddress(pkt->getAddr()); 296 (*msg).m_Sender = m_machineID; 297 298 SenderState *s = dynamic_cast<SenderState *>(pkt->senderState); 299 (*msg).m_OriginalRequestorMachId = s->id; 300 delete s; 301 302 if (pkt->isRead()) { 303 (*msg).m_Type = MemoryRequestType_MEMORY_READ; 304 (*msg).m_MessageSize = MessageSizeType_Response_Data; 305 306 // Copy data from the packet 307 (*msg).m_DataBlk.setData(pkt->getPtr<uint8_t>(), 0, 308 RubySystem::getBlockSizeBytes()); 309 } else if (pkt->isWrite()) { 310 (*msg).m_Type = MemoryRequestType_MEMORY_WB; 311 (*msg).m_MessageSize = MessageSizeType_Writeback_Control; 312 } else { 313 panic("Incorrect packet type received from memory controller!"); 314 } 315 316 m_responseFromMemory_ptr->enqueue(msg); 317 delete pkt; 318} 319 320bool 321AbstractController::MemoryPort::recvTimingResp(PacketPtr pkt) 322{ 323 controller->recvTimingResp(pkt); 324 return true; 325} 326 327AbstractController::MemoryPort::MemoryPort(const std::string &_name, 328 AbstractController *_controller, 329 const std::string &_label) 330 : QueuedMasterPort(_name, _controller, _queue), 331 _queue(*_controller, *this, _label), controller(_controller) 332{ 333} |
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