1/* |
2 * Copyright (c) 2017 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * |
14 * Copyright (c) 2011-2014 Mark D. Hill and David A. Wood 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright --- 28 unchanged lines hidden (view full) --- 50 51AbstractController::AbstractController(const Params *p) 52 : MemObject(p), Consumer(this), m_version(p->version), 53 m_clusterID(p->cluster_id), 54 m_masterId(p->system->getMasterId(name())), m_is_blocking(false), 55 m_number_of_TBEs(p->number_of_TBEs), 56 m_transitions_per_cycle(p->transitions_per_cycle), 57 m_buffer_size(p->buffer_size), m_recycle_latency(p->recycle_latency), |
58 memoryPort(csprintf("%s.memory", name()), this, ""), 59 addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()) |
60{ 61 if (m_version == 0) { 62 // Combine the statistics from all controllers 63 // of this particular type. 64 Stats::registerDumpCallback(new StatsCallback(this)); 65 } 66} 67 --- 287 unchanged lines hidden (view full) --- 355 panic("Incorrect packet type received from memory controller!"); 356 } 357 358 getMemoryQueue()->enqueue(msg, clockEdge(), cyclesToTicks(Cycles(1))); 359 delete pkt->req; 360 delete pkt; 361} 362 |
363MachineID 364AbstractController::mapAddressToMachine(Addr addr, MachineType mtype) const 365{ 366 NodeID node = m_net_ptr->addressToNodeID(addr, mtype); 367 MachineID mach = {mtype, node}; 368 return mach; 369} 370 |
371bool 372AbstractController::MemoryPort::recvTimingResp(PacketPtr pkt) 373{ 374 controller->recvTimingResp(pkt); 375 return true; 376} 377 378AbstractController::MemoryPort::MemoryPort(const std::string &_name, 379 AbstractController *_controller, 380 const std::string &_label) 381 : QueuedMasterPort(_name, _controller, reqQueue, snoopRespQueue), 382 reqQueue(*_controller, *this, _label), 383 snoopRespQueue(*_controller, *this, _label), 384 controller(_controller) 385{ 386} |