AbstractCacheEntry.hh (11032:dec9cb2c5cde) AbstractCacheEntry.hh (11049:dfb0aa3f0649)
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 42 unchanged lines hidden (view full) ---

51 // Get/Set permission of the entry
52 void changePermission(AccessPermission new_perm);
53
54 // The methods below are those called by ruby runtime, add when it
55 // is absolutely necessary and should all be virtual function.
56 virtual DataBlock& getDataBlk()
57 { panic("getDataBlk() not implemented!"); }
58
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 42 unchanged lines hidden (view full) ---

51 // Get/Set permission of the entry
52 void changePermission(AccessPermission new_perm);
53
54 // The methods below are those called by ruby runtime, add when it
55 // is absolutely necessary and should all be virtual function.
56 virtual DataBlock& getDataBlk()
57 { panic("getDataBlk() not implemented!"); }
58
59 // Functions for locking and unlocking the cache entry. These are required
60 // for supporting atomic memory accesses.
61 void setLocked(int context);
62 void clearLocked();
63 bool isLocked(int context) const;
64
59
65 void setSetIndex(uint32_t s) { m_set_index = s; }
66 uint32_t getSetIndex() const { return m_set_index; }
67
68 void setWayIndex(uint32_t s) { m_way_index = s; }
69 uint32_t getWayIndex() const { return m_way_index; }
70
71 // Address of this block, required by CacheMemory
72 Addr m_Address;
73 // Holds info whether the address is locked.
74 // Required for implementing LL/SC operations.
75 int m_locked;
76
77 private:
78 // Set and way coordinates of the entry within the cache memory object.
79 uint32_t m_set_index;
80 uint32_t m_way_index;
60 Addr m_Address; // Address of this block, required by CacheMemory
61 int m_locked; // Holds info whether the address is locked,
62 // required for implementing LL/SC
81};
82
83inline std::ostream&
84operator<<(std::ostream& out, const AbstractCacheEntry& obj)
85{
86 obj.print(out);
87 out << std::flush;
88 return out;
89}
90
91#endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCACHEENTRY_HH__
63};
64
65inline std::ostream&
66operator<<(std::ostream& out, const AbstractCacheEntry& obj)
67{
68 obj.print(out);
69 out << std::flush;
70 return out;
71}
72
73#endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCACHEENTRY_HH__