1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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30 * Common base class for a machine node.
31 */
32
33#ifndef __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCACHEENTRY_HH__
34#define __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCACHEENTRY_HH__
35
36#include <iostream>
37
38#include "mem/protocol/AccessPermission.hh"
39#include "mem/ruby/common/Address.hh"
40#include "mem/ruby/slicc_interface/AbstractEntry.hh"
41
42class DataBlock;
43
44class AbstractCacheEntry : public AbstractEntry
45{
46 public:
47 AbstractCacheEntry();
48 virtual ~AbstractCacheEntry() = 0;
49
50 // Get/Set permission of the entry
51 void changePermission(AccessPermission new_perm);
52
53 Address m_Address; // Address of this block, required by CacheMemory
54 int m_locked; // Holds info whether the address is locked,
55 // required for implementing LL/SC
56};
57
58inline std::ostream&
59operator<<(std::ostream& out, const AbstractCacheEntry& obj)
60{
61 obj.print(out);
62 out << std::flush;
63 return out;
64}
65
66#endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCACHEENTRY_HH__