1/* 2 * Copyright (c) 2019 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 700 unchanged lines hidden (view full) --- 709 else { 710 trigger(Event:L1_PUTS, in_msg.addr, 711 cache_entry, TBEs[in_msg.addr]); 712 } 713 } else if (in_msg.Type == CoherenceRequestType:WRITEBACK_DIRTY_DATA) { 714 Entry cache_entry := getCacheEntry(in_msg.addr); 715 if (is_invalid(cache_entry) && 716 L2cache.cacheAvail(in_msg.addr) == false) { |
717 Addr victim := L2cache.cacheProbe(in_msg.addr); 718 trigger(Event:L2_Replacement, 719 victim, getCacheEntry(victim), TBEs[victim]); |
720 } 721 else { 722 trigger(Event:L1_WBDIRTYDATA, in_msg.addr, 723 cache_entry, TBEs[in_msg.addr]); 724 } 725 } else if (in_msg.Type == CoherenceRequestType:WRITEBACK_CLEAN_DATA) { 726 Entry cache_entry := getCacheEntry(in_msg.addr); 727 if (is_invalid(cache_entry) && 728 L2cache.cacheAvail(in_msg.addr) == false) { |
729 Addr victim := L2cache.cacheProbe(in_msg.addr); 730 trigger(Event:L2_Replacement, 731 victim, getCacheEntry(victim), TBEs[victim]); |
732 } 733 else { 734 trigger(Event:L1_WBCLEANDATA, in_msg.addr, 735 cache_entry, TBEs[in_msg.addr]); 736 } 737 } else { 738 error("Unexpected message"); 739 } --- 2185 unchanged lines hidden --- |