MESI_Two_Level-L1cache.sm (14184:11ac1337c5e2) MESI_Two_Level-L1cache.sm (14300:22183ae13998)
1/*
2 * Copyright (c) 1999-2013 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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325 if (L1Icache.cacheAvail(in_msg.LineAddress)) {
326 // L1 does't have the line, but we have space for it
327 // in the L1 so let's see if the L2 has it
328 trigger(prefetch_request_type_to_event(in_msg.Type),
329 in_msg.LineAddress,
330 L1Icache_entry, TBEs[in_msg.LineAddress]);
331 } else {
332 // No room in the L1, so we need to make room in the L1
1/*
2 * Copyright (c) 1999-2013 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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325 if (L1Icache.cacheAvail(in_msg.LineAddress)) {
326 // L1 does't have the line, but we have space for it
327 // in the L1 so let's see if the L2 has it
328 trigger(prefetch_request_type_to_event(in_msg.Type),
329 in_msg.LineAddress,
330 L1Icache_entry, TBEs[in_msg.LineAddress]);
331 } else {
332 // No room in the L1, so we need to make room in the L1
333 Addr victim := L1Icache.cacheProbe(in_msg.LineAddress);
333 trigger(Event:PF_L1_Replacement,
334 trigger(Event:PF_L1_Replacement,
334 L1Icache.cacheProbe(in_msg.LineAddress),
335 getL1ICacheEntry(L1Icache.cacheProbe(in_msg.LineAddress)),
336 TBEs[L1Icache.cacheProbe(in_msg.LineAddress)]);
335 victim, getL1ICacheEntry(victim), TBEs[victim]);
337 }
338 } else {
339 // Data prefetch
340 Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
341 if (is_valid(L1Dcache_entry)) {
342 // The block to be prefetched is already present in the
343 // cache. We should drop this request.
344 trigger(prefetch_request_type_to_event(in_msg.Type),

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359 if (L1Dcache.cacheAvail(in_msg.LineAddress)) {
360 // L1 does't have the line, but we have space for it in
361 // the L1 let's see if the L2 has it
362 trigger(prefetch_request_type_to_event(in_msg.Type),
363 in_msg.LineAddress,
364 L1Dcache_entry, TBEs[in_msg.LineAddress]);
365 } else {
366 // No room in the L1, so we need to make room in the L1
336 }
337 } else {
338 // Data prefetch
339 Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
340 if (is_valid(L1Dcache_entry)) {
341 // The block to be prefetched is already present in the
342 // cache. We should drop this request.
343 trigger(prefetch_request_type_to_event(in_msg.Type),

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358 if (L1Dcache.cacheAvail(in_msg.LineAddress)) {
359 // L1 does't have the line, but we have space for it in
360 // the L1 let's see if the L2 has it
361 trigger(prefetch_request_type_to_event(in_msg.Type),
362 in_msg.LineAddress,
363 L1Dcache_entry, TBEs[in_msg.LineAddress]);
364 } else {
365 // No room in the L1, so we need to make room in the L1
366 Addr victim := L1Dcache.cacheProbe(in_msg.LineAddress);
367 trigger(Event:PF_L1_Replacement,
367 trigger(Event:PF_L1_Replacement,
368 L1Dcache.cacheProbe(in_msg.LineAddress),
369 getL1DCacheEntry(L1Dcache.cacheProbe(in_msg.LineAddress)),
370 TBEs[L1Dcache.cacheProbe(in_msg.LineAddress)]);
368 victim, getL1DCacheEntry(victim), TBEs[victim]);
371 }
372 }
373 }
374 }
375 }
376
377 // Response L1 Network - response msg to this L1 cache
378 in_port(responseL1Network_in, ResponseMsg, responseToL1Cache, rank = 2) {

--- 1056 unchanged lines hidden --- 		369 }
370 }
371 }
372 }
373 }
374
375 // Response L1 Network - response msg to this L1 cache
376 in_port(responseL1Network_in, ResponseMsg, responseToL1Cache, rank = 2) {

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