Profiler.hh (9747:fbe79534d024) | Profiler.hh (9773:915be89faf30) |
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1/* 2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 38 unchanged lines hidden (view full) --- 47 48#include <iostream> 49#include <map> 50#include <string> 51#include <vector> 52 53#include "base/hashmap.hh" 54#include "mem/protocol/AccessType.hh" | 1/* 2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 38 unchanged lines hidden (view full) --- 47 48#include <iostream> 49#include <map> 50#include <string> 51#include <vector> 52 53#include "base/hashmap.hh" 54#include "mem/protocol/AccessType.hh" |
55#include "mem/protocol/GenericMachineType.hh" | |
56#include "mem/protocol/PrefetchBit.hh" 57#include "mem/protocol/RubyAccessMode.hh" 58#include "mem/protocol/RubyRequestType.hh" 59#include "mem/ruby/common/Address.hh" 60#include "mem/ruby/common/Global.hh" 61#include "mem/ruby/common/Histogram.hh" 62#include "mem/ruby/common/Set.hh" 63#include "mem/ruby/system/MachineID.hh" --- 41 unchanged lines hidden (view full) --- 105 void 106 profileAverageLatencyEstimate(int latency) 107 { 108 m_average_latency_estimate.add(latency); 109 } 110 111 void controllerBusy(MachineID machID); 112 void bankBusy(); | 55#include "mem/protocol/PrefetchBit.hh" 56#include "mem/protocol/RubyAccessMode.hh" 57#include "mem/protocol/RubyRequestType.hh" 58#include "mem/ruby/common/Address.hh" 59#include "mem/ruby/common/Global.hh" 60#include "mem/ruby/common/Histogram.hh" 61#include "mem/ruby/common/Set.hh" 62#include "mem/ruby/system/MachineID.hh" --- 41 unchanged lines hidden (view full) --- 104 void 105 profileAverageLatencyEstimate(int latency) 106 { 107 m_average_latency_estimate.add(latency); 108 } 109 110 void controllerBusy(MachineID machID); 111 void bankBusy(); |
113 114 void missLatency(Cycles t, RubyRequestType type, 115 const GenericMachineType respondingMach); 116 117 void missLatencyWcc(Cycles issuedTime, Cycles initialRequestTime, 118 Cycles forwardRequestTime, Cycles firstResponseTime, 119 Cycles completionTime); | |
120 | 112 |
121 void missLatencyDir(Cycles issuedTime, Cycles initialRequestTime, 122 Cycles forwardRequestTime, Cycles firstResponseTime, 123 Cycles completionTime); 124 125 void swPrefetchLatency(Cycles t, RubyRequestType type, 126 const GenericMachineType respondingMach); 127 | |
128 void print(std::ostream& out) const; 129 130 void rubyWatch(int proc); 131 bool watchAddress(Address addr); 132 133 // return Ruby's start time 134 Cycles getRubyStartTime() { return m_ruby_start; } 135 136 // added by SS 137 bool getHotLines() { return m_hot_lines; } 138 bool getAllInstructions() { return m_all_instructions; } 139 140 private: 141 void printRequestProfile(std::ostream &out) const; 142 void printDelayProfile(std::ostream &out) const; 143 void printOutstandingReqProfile(std::ostream &out) const; | 113 void print(std::ostream& out) const; 114 115 void rubyWatch(int proc); 116 bool watchAddress(Address addr); 117 118 // return Ruby's start time 119 Cycles getRubyStartTime() { return m_ruby_start; } 120 121 // added by SS 122 bool getHotLines() { return m_hot_lines; } 123 bool getAllInstructions() { return m_all_instructions; } 124 125 private: 126 void printRequestProfile(std::ostream &out) const; 127 void printDelayProfile(std::ostream &out) const; 128 void printOutstandingReqProfile(std::ostream &out) const; |
129 void printMissLatencyProfile(std::ostream &out) const; |
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144 145 private: 146 // Private copy constructor and assignment operator 147 Profiler(const Profiler& obj); 148 Profiler& operator=(const Profiler& obj); 149 150 AddressProfiler* m_address_profiler_ptr; 151 AddressProfiler* m_inst_profiler_ptr; --- 4 unchanged lines hidden (view full) --- 156 int64_t m_busyBankCount; 157 158 Histogram m_read_sharing_histogram; 159 Histogram m_write_sharing_histogram; 160 Histogram m_all_sharing_histogram; 161 int64 m_cache_to_cache; 162 int64 m_memory_to_cache; 163 | 130 131 private: 132 // Private copy constructor and assignment operator 133 Profiler(const Profiler& obj); 134 Profiler& operator=(const Profiler& obj); 135 136 AddressProfiler* m_address_profiler_ptr; 137 AddressProfiler* m_inst_profiler_ptr; --- 4 unchanged lines hidden (view full) --- 142 int64_t m_busyBankCount; 143 144 Histogram m_read_sharing_histogram; 145 Histogram m_write_sharing_histogram; 146 Histogram m_all_sharing_histogram; 147 int64 m_cache_to_cache; 148 int64 m_memory_to_cache; 149 |
164 std::vector<Histogram> m_missLatencyHistograms; 165 std::vector<Histogram> m_machLatencyHistograms; 166 std::vector< std::vector<Histogram> > m_missMachLatencyHistograms; 167 Histogram m_wCCIssueToInitialRequestHistogram; 168 Histogram m_wCCInitialRequestToForwardRequestHistogram; 169 Histogram m_wCCForwardRequestToFirstResponseHistogram; 170 Histogram m_wCCFirstResponseToCompleteHistogram; 171 int64 m_wCCIncompleteTimes; 172 Histogram m_dirIssueToInitialRequestHistogram; 173 Histogram m_dirInitialRequestToForwardRequestHistogram; 174 Histogram m_dirForwardRequestToFirstResponseHistogram; 175 Histogram m_dirFirstResponseToCompleteHistogram; 176 int64 m_dirIncompleteTimes; 177 178 Histogram m_allMissLatencyHistogram; 179 180 Histogram m_allSWPrefetchLatencyHistogram; 181 Histogram m_SWPrefetchL2MissLatencyHistogram; 182 std::vector<Histogram> m_SWPrefetchLatencyHistograms; 183 std::vector<Histogram> m_SWPrefetchMachLatencyHistograms; 184 | |
185 Histogram m_average_latency_estimate; 186 m5::hash_set<Address> m_watch_address_set; 187 188 //added by SS 189 bool m_hot_lines; 190 bool m_all_instructions; 191 192 int m_num_of_sequencers; 193}; 194 195inline std::ostream& 196operator<<(std::ostream& out, const Profiler& obj) 197{ 198 obj.print(out); 199 out << std::flush; 200 return out; 201} 202 203#endif // __MEM_RUBY_PROFILER_PROFILER_HH__ | 150 Histogram m_average_latency_estimate; 151 m5::hash_set<Address> m_watch_address_set; 152 153 //added by SS 154 bool m_hot_lines; 155 bool m_all_instructions; 156 157 int m_num_of_sequencers; 158}; 159 160inline std::ostream& 161operator<<(std::ostream& out, const Profiler& obj) 162{ 163 obj.print(out); 164 out << std::flush; 165 return out; 166} 167 168#endif // __MEM_RUBY_PROFILER_PROFILER_HH__ |