Profiler.hh (9497:2759161b9d7f) Profiler.hh (9507:d2ab6d889fc7)
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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120 {
121 m_average_latency_estimate.add(latency);
122 }
123
124 void recordPrediction(bool wasGood, bool wasPredicted);
125
126 void startTransaction(int cpu);
127 void endTransaction(int cpu);
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 111 unchanged lines hidden (view full) ---

120 {
121 m_average_latency_estimate.add(latency);
122 }
123
124 void recordPrediction(bool wasGood, bool wasPredicted);
125
126 void startTransaction(int cpu);
127 void endTransaction(int cpu);
128 void profilePFWait(Time waitTime);
128 void profilePFWait(Cycles waitTime);
129
130 void controllerBusy(MachineID machID);
131 void bankBusy();
132
129
130 void controllerBusy(MachineID machID);
131 void bankBusy();
132
133 void missLatency(Time t,
134 RubyRequestType type,
133 void missLatency(Cycles t, RubyRequestType type,
135 const GenericMachineType respondingMach);
136
134 const GenericMachineType respondingMach);
135
137 void missLatencyWcc(Time issuedTime,
138 Time initialRequestTime,
139 Time forwardRequestTime,
140 Time firstResponseTime,
141 Time completionTime);
136 void missLatencyWcc(Cycles issuedTime, Cycles initialRequestTime,
137 Cycles forwardRequestTime, Cycles firstResponseTime,
138 Cycles completionTime);
142
139
143 void missLatencyDir(Time issuedTime,
144 Time initialRequestTime,
145 Time forwardRequestTime,
146 Time firstResponseTime,
147 Time completionTime);
140 void missLatencyDir(Cycles issuedTime, Cycles initialRequestTime,
141 Cycles forwardRequestTime, Cycles firstResponseTime,
142 Cycles completionTime);
148
143
149 void swPrefetchLatency(Time t,
150 RubyRequestType type,
144 void swPrefetchLatency(Cycles t, RubyRequestType type,
151 const GenericMachineType respondingMach);
152
153 void sequencerRequests(int num) { m_sequencer_requests.add(num); }
154
155 void print(std::ostream& out) const;
156
157 void rubyWatch(int proc);
158 bool watchAddress(Address addr);
159
160 // return Ruby's start time
145 const GenericMachineType respondingMach);
146
147 void sequencerRequests(int num) { m_sequencer_requests.add(num); }
148
149 void print(std::ostream& out) const;
150
151 void rubyWatch(int proc);
152 bool watchAddress(Address addr);
153
154 // return Ruby's start time
161 Time
162 getRubyStartTime()
163 {
164 return m_ruby_start;
165 }
155 Cycles getRubyStartTime() { return m_ruby_start; }
166
167 // added by SS
168 bool getHotLines() { return m_hot_lines; }
169 bool getAllInstructions() { return m_all_instructions; }
170
171 private:
172 void printRequestProfile(std::ostream &out);
173 void printDelayProfile(std::ostream &out);

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181 AddressProfiler* m_inst_profiler_ptr;
182
183 std::vector<int64> m_instructions_executed_at_start;
184 std::vector<int64> m_cycles_executed_at_start;
185
186 std::ostream* m_periodic_output_file_ptr;
187 int64_t m_stats_period;
188
156
157 // added by SS
158 bool getHotLines() { return m_hot_lines; }
159 bool getAllInstructions() { return m_all_instructions; }
160
161 private:
162 void printRequestProfile(std::ostream &out);
163 void printDelayProfile(std::ostream &out);

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171 AddressProfiler* m_inst_profiler_ptr;
172
173 std::vector<int64> m_instructions_executed_at_start;
174 std::vector<int64> m_cycles_executed_at_start;
175
176 std::ostream* m_periodic_output_file_ptr;
177 int64_t m_stats_period;
178
189 Time m_ruby_start;
179 Cycles m_ruby_start;
190 time_t m_real_time_start_time;
191
192 int64_t m_busyBankCount;
193 Histogram m_multicast_retry_histogram;
194
195 Histogram m_filter_action_histogram;
196 Histogram m_tbeProfile;
197

--- 67 unchanged lines hidden --- 		180 time_t m_real_time_start_time;
181
182 int64_t m_busyBankCount;
183 Histogram m_multicast_retry_histogram;
184
185 Histogram m_filter_action_histogram;
186 Histogram m_tbeProfile;
187

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