Profiler.hh (7546:84e8f914b3b8) Profiler.hh (7565:9fc3475e8175)
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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133
134 void controllerBusy(MachineID machID);
135 void bankBusy();
136
137 void missLatency(Time t,
138 RubyRequestType type,
139 const GenericMachineType respondingMach);
140
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 124 unchanged lines hidden (view full) ---

133
134 void controllerBusy(MachineID machID);
135 void bankBusy();
136
137 void missLatency(Time t,
138 RubyRequestType type,
139 const GenericMachineType respondingMach);
140
141 void missLatencyWcc(Time issuedTime,
142 Time initialRequestTime,
143 Time forwardRequestTime,
144 Time firstResponseTime,
145 Time completionTime);
146
147 void missLatencyDir(Time issuedTime,
148 Time initialRequestTime,
149 Time forwardRequestTime,
150 Time firstResponseTime,
151 Time completionTime);
152
141 void swPrefetchLatency(Time t,
142 CacheRequestType type,
143 const GenericMachineType respondingMach);
144
145 void sequencerRequests(int num) { m_sequencer_requests.add(num); }
146
147 void profileTransition(const std::string& component, NodeID version,
148 Address addr, const std::string& state, const std::string& event,

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195 Histogram m_all_sharing_histogram;
196 int64 m_cache_to_cache;
197 int64 m_memory_to_cache;
198
199 Histogram m_prefetchWaitHistogram;
200
201 std::vector<Histogram> m_missLatencyHistograms;
202 std::vector<Histogram> m_machLatencyHistograms;
153 void swPrefetchLatency(Time t,
154 CacheRequestType type,
155 const GenericMachineType respondingMach);
156
157 void sequencerRequests(int num) { m_sequencer_requests.add(num); }
158
159 void profileTransition(const std::string& component, NodeID version,
160 Address addr, const std::string& state, const std::string& event,

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207 Histogram m_all_sharing_histogram;
208 int64 m_cache_to_cache;
209 int64 m_memory_to_cache;
210
211 Histogram m_prefetchWaitHistogram;
212
213 std::vector<Histogram> m_missLatencyHistograms;
214 std::vector<Histogram> m_machLatencyHistograms;
215 std::vector< std::vector<Histogram> > m_missMachLatencyHistograms;
216 Histogram m_wCCIssueToInitialRequestHistogram;
217 Histogram m_wCCInitialRequestToForwardRequestHistogram;
218 Histogram m_wCCForwardRequestToFirstResponseHistogram;
219 Histogram m_wCCFirstResponseToCompleteHistogram;
220 int64 m_wCCIncompleteTimes;
221 Histogram m_dirIssueToInitialRequestHistogram;
222 Histogram m_dirInitialRequestToForwardRequestHistogram;
223 Histogram m_dirForwardRequestToFirstResponseHistogram;
224 Histogram m_dirFirstResponseToCompleteHistogram;
225 int64 m_dirIncompleteTimes;
226
203 Histogram m_allMissLatencyHistogram;
204
205 Histogram m_allSWPrefetchLatencyHistogram;
206 Histogram m_SWPrefetchL2MissLatencyHistogram;
207 std::vector<Histogram> m_SWPrefetchLatencyHistograms;
208 std::vector<Histogram> m_SWPrefetchMachLatencyHistograms;
209
210 Histogram m_delayedCyclesHistogram;

--- 31 unchanged lines hidden --- 		227 Histogram m_allMissLatencyHistogram;
228
229 Histogram m_allSWPrefetchLatencyHistogram;
230 Histogram m_SWPrefetchL2MissLatencyHistogram;
231 std::vector<Histogram> m_SWPrefetchLatencyHistograms;
232 std::vector<Histogram> m_SWPrefetchMachLatencyHistograms;
233
234 Histogram m_delayedCyclesHistogram;

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