1/* 2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 33 unchanged lines hidden (view full) --- 42 ---------------------------------------------------------------------- 43*/ 44 45#ifndef __MEM_RUBY_PROFILER_PROFILER_HH__ 46#define __MEM_RUBY_PROFILER_PROFILER_HH__ 47 48#include <iostream> 49#include <string> |
50#include <vector> |
51 52#include "mem/protocol/AccessModeType.hh" 53#include "mem/protocol/AccessType.hh" 54#include "mem/protocol/CacheRequestType.hh" 55#include "mem/protocol/GenericMachineType.hh" 56#include "mem/protocol/GenericRequestType.hh" 57#include "mem/protocol/PrefetchBit.hh" 58#include "mem/ruby/common/Address.hh" --- 103 unchanged lines hidden (view full) --- 162 private: 163 // Private copy constructor and assignment operator 164 Profiler(const Profiler& obj); 165 Profiler& operator=(const Profiler& obj); 166 167 AddressProfiler* m_address_profiler_ptr; 168 AddressProfiler* m_inst_profiler_ptr; 169 |
170 std::vector<int64> m_instructions_executed_at_start; 171 std::vector<int64> m_cycles_executed_at_start; |
172 173 std::ostream* m_periodic_output_file_ptr; 174 integer_t m_stats_period; 175 176 Time m_ruby_start; 177 time_t m_real_time_start_time; 178 |
179 std::vector<std::vector<integer_t> > m_busyControllerCount; |
180 integer_t m_busyBankCount; 181 Histogram m_multicast_retry_histogram; 182 183 Histogram m_filter_action_histogram; 184 Histogram m_tbeProfile; 185 186 Histogram m_sequencer_requests; 187 Histogram m_read_sharing_histogram; 188 Histogram m_write_sharing_histogram; 189 Histogram m_all_sharing_histogram; 190 int64 m_cache_to_cache; 191 int64 m_memory_to_cache; 192 193 Histogram m_prefetchWaitHistogram; 194 |
195 std::vector<Histogram> m_missLatencyHistograms; 196 std::vector<Histogram> m_machLatencyHistograms; |
197 Histogram m_allMissLatencyHistogram; 198 199 Histogram m_allSWPrefetchLatencyHistogram; 200 Histogram m_SWPrefetchL2MissLatencyHistogram; |
201 std::vector<Histogram> m_SWPrefetchLatencyHistograms; 202 std::vector<Histogram> m_SWPrefetchMachLatencyHistograms; |
203 204 Histogram m_delayedCyclesHistogram; 205 Histogram m_delayedCyclesNonPFHistogram; |
206 std::vector<Histogram> m_delayedCyclesVCHistograms; |
207 208 Histogram m_outstanding_requests; 209 Histogram m_outstanding_persistent_requests; 210 211 Histogram m_average_latency_estimate; 212 213 Map<Address, int>* m_watch_address_list_ptr; 214 // counts all initiated cache request including PUTs --- 21 unchanged lines hidden --- |