1/* 2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 66 unchanged lines hidden (view full) --- 75#include "sim/sim_object.hh" 76 77class CacheMsg; 78class AddressProfiler; 79 80template <class KEY_TYPE, class VALUE_TYPE> class Map; 81 82struct memory_control_profiler { |
83 uint64 m_memReq; 84 uint64 m_memBankBusy; 85 uint64 m_memBusBusy; 86 uint64 m_memTfawBusy; 87 uint64 m_memReadWriteBusy; 88 uint64 m_memDataBusBusy; 89 uint64 m_memRefresh; 90 uint64 m_memRead; 91 uint64 m_memWrite; 92 uint64 m_memWaitCycles; 93 uint64 m_memInputQ; 94 uint64 m_memBankQ; 95 uint64 m_memArbWait; 96 uint64 m_memRandBusy; 97 uint64 m_memNotOld; 98 Vector<uint64> m_memBankCount; |
99 int m_banks_per_rank; 100 int m_ranks_per_dimm; 101 int m_dimms_per_channel; 102}; 103 104 105class Profiler : public SimObject, public Consumer { 106public: 107 // Constructors 108 typedef RubyProfilerParams Params; 109 Profiler(const Params *); 110 |
111 // Destructor 112 ~Profiler(); 113 114 // Public Methods 115 void wakeup(); 116 117 void setPeriodicStatsFile(const string& filename); 118 void setPeriodicStatsInterval(integer_t period); --- 47 unchanged lines hidden (view full) --- 166 bool watchAddress(Address addr); 167 168 // return Ruby's start time 169 Time getRubyStartTime(){ 170 return m_ruby_start; 171 } 172 173 // added for MemoryControl: |
174 void profileMemReq(int mem_cntrl, int bank); 175 void profileMemBankBusy(int mem_cntrl); 176 void profileMemBusBusy(int mem_cntrl); 177 void profileMemTfawBusy(int mem_cntrl); 178 void profileMemReadWriteBusy(int mem_cntrl); 179 void profileMemDataBusBusy(int mem_cntrl); 180 void profileMemRefresh(int mem_cntrl); 181 void profileMemRead(int mem_cntrl); 182 void profileMemWrite(int mem_cntrl); 183 void profileMemWaitCycles(int mem_cntrl, int cycles); 184 void profileMemInputQ(int mem_cntrl, int cycles); 185 void profileMemBankQ(int mem_cntrl, int cycles); 186 void profileMemArbWait(int mem_cntrl, int cycles); 187 void profileMemRandBusy(int mem_cntrl); 188 void profileMemNotOld(int mem_cntrl); |
189 //added by SS 190 bool getHotLines() { return m_hot_lines; } 191 bool getAllInstructions() { return m_all_instructions; } 192 193private: 194 //added by SS 195 vector<string> m_memory_control_names; 196 --- 55 unchanged lines hidden (view full) --- 252 253 Map<Address, int>* m_watch_address_list_ptr; 254 // counts all initiated cache request including PUTs 255 int m_requests; 256 Map <string, int>* m_requestProfileMap_ptr; 257 258 // added for MemoryControl: 259 //added by SS |
260 Vector < memory_control_profiler* > m_mc_profilers; |
261 262 //added by SS 263 bool m_hot_lines; 264 bool m_all_instructions; 265}; 266 267// Output operator declaration 268ostream& operator<<(ostream& out, const Profiler& obj); --- 15 unchanged lines hidden --- |