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< struct memory_control_profiler {
< uint64 m_memReq;
< uint64 m_memBankBusy;
< uint64 m_memBusBusy;
< uint64 m_memTfawBusy;
< uint64 m_memReadWriteBusy;
< uint64 m_memDataBusBusy;
< uint64 m_memRefresh;
< uint64 m_memRead;
< uint64 m_memWrite;
< uint64 m_memWaitCycles;
< uint64 m_memInputQ;
< uint64 m_memBankQ;
< uint64 m_memArbWait;
< uint64 m_memRandBusy;
< uint64 m_memNotOld;
< Vector<uint64> m_memBankCount;
< int m_banks_per_rank;
< int m_ranks_per_dimm;
< int m_dimms_per_channel;
< };
<
<
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< // added for MemoryControl:
< void profileMemReq(int mem_cntrl, int bank);
< void profileMemBankBusy(int mem_cntrl);
< void profileMemBusBusy(int mem_cntrl);
< void profileMemTfawBusy(int mem_cntrl);
< void profileMemReadWriteBusy(int mem_cntrl);
< void profileMemDataBusBusy(int mem_cntrl);
< void profileMemRefresh(int mem_cntrl);
< void profileMemRead(int mem_cntrl);
< void profileMemWrite(int mem_cntrl);
< void profileMemWaitCycles(int mem_cntrl, int cycles);
< void profileMemInputQ(int mem_cntrl, int cycles);
< void profileMemBankQ(int mem_cntrl, int cycles);
< void profileMemArbWait(int mem_cntrl, int cycles);
< void profileMemRandBusy(int mem_cntrl);
< void profileMemNotOld(int mem_cntrl);
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< //added by SS
< vector<string> m_memory_control_names;
258d216
< // added for MemoryControl:
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< Vector < memory_control_profiler* > m_mc_profilers;
<
< //added by SS