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> #include "mem/ruby/libruby.hh"
>
70a73
> #include "mem/ruby/system/MemoryControl.hh"
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> struct memory_control_profiler {
> long long int m_memReq;
> long long int m_memBankBusy;
> long long int m_memBusBusy;
> long long int m_memTfawBusy;
> long long int m_memReadWriteBusy;
> long long int m_memDataBusBusy;
> long long int m_memRefresh;
> long long int m_memRead;
> long long int m_memWrite;
> long long int m_memWaitCycles;
> long long int m_memInputQ;
> long long int m_memBankQ;
> long long int m_memArbWait;
> long long int m_memRandBusy;
> long long int m_memNotOld;
> Vector<long long int> m_memBankCount;
> int m_banks_per_rank;
> int m_ranks_per_dimm;
> int m_dimms_per_channel;
> };
>
>
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< // Constructors
< Profiler();
---
> // Constructors
> Profiler(const string & name);
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< // Destructor
< ~Profiler();
---
> void init(const vector<string> & argv, vector<string> memory_control_names);
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< // Public Methods
< void wakeup();
---
> // Destructor
> ~Profiler();
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< void setPeriodicStatsFile(const string& filename);
< void setPeriodicStatsInterval(integer_t period);
---
> // Public Methods
> void wakeup();
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< void printStats(ostream& out, bool short_stats=false);
< void printShortStats(ostream& out) { printStats(out, true); }
< void printTraceStats(ostream& out) const;
< void clearStats();
< void printConfig(ostream& out) const;
< void printResourceUsage(ostream& out) const;
---
> void setPeriodicStatsFile(const string& filename);
> void setPeriodicStatsInterval(integer_t period);
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< AddressProfiler* getAddressProfiler() { return m_address_profiler_ptr; }
< AddressProfiler* getInstructionProfiler() { return m_inst_profiler_ptr; }
---
> void printStats(ostream& out, bool short_stats=false);
> void printShortStats(ostream& out) { printStats(out, true); }
> void printTraceStats(ostream& out) const;
> void clearStats();
> void printConfig(ostream& out) const;
> void printResourceUsage(ostream& out) const;
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< void addPrimaryStatSample(const CacheMsg& msg, NodeID id);
< void addSecondaryStatSample(GenericRequestType requestType,
< AccessModeType type, int msgSize,
< PrefetchBit pfBit, NodeID id);
< void addSecondaryStatSample(CacheRequestType requestType,
< AccessModeType type, int msgSize,
< PrefetchBit pfBit, NodeID id);
< void addAddressTraceSample(const CacheMsg& msg, NodeID id);
---
> AddressProfiler* getAddressProfiler() { return m_address_profiler_ptr; }
> AddressProfiler* getInstructionProfiler() { return m_inst_profiler_ptr; }
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< void profileRequest(const string& requestStr);
< void profileSharing(const Address& addr, AccessType type,
< NodeID requestor, const Set& sharers,
< const Set& owner);
---
> void addPrimaryStatSample(const CacheMsg& msg, NodeID id);
> void addSecondaryStatSample(GenericRequestType requestType, AccessModeType type, int msgSize, PrefetchBit pfBit, NodeID id);
> void addSecondaryStatSample(CacheRequestType requestType, AccessModeType type, int msgSize, PrefetchBit pfBit, NodeID id);
> void addAddressTraceSample(const CacheMsg& msg, NodeID id);
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< void profileMulticastRetry(const Address& addr, int count);
---
> void profileRequest(const string& requestStr);
> void profileSharing(const Address& addr, AccessType type, NodeID requestor, const Set& sharers, const Set& owner);
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< void profileFilterAction(int action);
---
> void profileMulticastRetry(const Address& addr, int count);
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< void profileConflictingRequests(const Address& addr);
< void profileOutstandingRequest(int outstanding) {
< m_outstanding_requests.add(outstanding);
< }
---
> void profileFilterAction(int action);
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< void profileOutstandingPersistentRequest(int outstanding) {
< m_outstanding_persistent_requests.add(outstanding);
< }
< void profileAverageLatencyEstimate(int latency) {
< m_average_latency_estimate.add(latency);
< }
---
> void profileConflictingRequests(const Address& addr);
> void profileOutstandingRequest(int outstanding) { m_outstanding_requests.add(outstanding); }
> void profileOutstandingPersistentRequest(int outstanding) { m_outstanding_persistent_requests.add(outstanding); }
> void profileAverageLatencyEstimate(int latency) { m_average_latency_estimate.add(latency); }
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< void countBAUnicast() { m_num_BA_unicasts++; }
< void countBABroadcast() { m_num_BA_broadcasts++; }
---
> void countBAUnicast() { m_num_BA_unicasts++; }
> void countBABroadcast() { m_num_BA_broadcasts++; }
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< void recordPrediction(bool wasGood, bool wasPredicted);
---
> void recordPrediction(bool wasGood, bool wasPredicted);
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< void startTransaction(int cpu);
< void endTransaction(int cpu);
< void profilePFWait(Time waitTime);
---
> void startTransaction(int cpu);
> void endTransaction(int cpu);
> void profilePFWait(Time waitTime);
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< void controllerBusy(MachineID machID);
< void bankBusy();
< void missLatency(Time t, CacheRequestType type,
< GenericMachineType respondingMach);
< void swPrefetchLatency(Time t, CacheRequestType type,
< GenericMachineType respondingMach);
< void stopTableUsageSample(int num) { m_stopTableProfile.add(num); }
< void L1tbeUsageSample(int num) { m_L1tbeProfile.add(num); }
< void L2tbeUsageSample(int num) { m_L2tbeProfile.add(num); }
< void sequencerRequests(int num) { m_sequencer_requests.add(num); }
< void storeBuffer(int size, int blocks) {
< m_store_buffer_size.add(size);
< m_store_buffer_blocks.add(blocks);
< }
---
> void controllerBusy(MachineID machID);
> void bankBusy();
> void missLatency(Time t, RubyRequestType type);
> void swPrefetchLatency(Time t, CacheRequestType type, GenericMachineType respondingMach);
> void stopTableUsageSample(int num) { m_stopTableProfile.add(num); }
> void L1tbeUsageSample(int num) { m_L1tbeProfile.add(num); }
> void L2tbeUsageSample(int num) { m_L2tbeProfile.add(num); }
> void sequencerRequests(int num) { m_sequencer_requests.add(num); }
> void storeBuffer(int size, int blocks) { m_store_buffer_size.add(size); m_store_buffer_blocks.add(blocks);}
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< void profileGetXMaskPrediction(const Set& pred_set);
< void profileGetSMaskPrediction(const Set& pred_set);
< void profileTrainingMask(const Set& pred_set);
< void profileTransition(const string& component, NodeID id, NodeID version,
< Address addr, const string& state,
< const string& event, const string& next_state,
< const string& note);
< void profileMsgDelay(int virtualNetwork, int delayCycles);
---
> void profileGetXMaskPrediction(const Set& pred_set);
> void profileGetSMaskPrediction(const Set& pred_set);
> void profileTrainingMask(const Set& pred_set);
> void profileTransition(const string& component, NodeID version, Address addr,
> const string& state, const string& event,
> const string& next_state, const string& note);
> void profileMsgDelay(int virtualNetwork, int delayCycles);
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< void print(ostream& out) const;
---
> void print(ostream& out) const;
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< int64 getTotalInstructionsExecuted() const;
< int64 getTotalTransactionsExecuted() const;
---
> int64 getTotalInstructionsExecuted() const;
> int64 getTotalTransactionsExecuted() const;
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< Time getRubyStartTime(){
< return m_ruby_start;
< }
---
> void rubyWatch(int proc);
> bool watchAddress(Address addr);
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< // added for MemoryControl:
< void profileMemReq(int bank);
< void profileMemBankBusy();
< void profileMemBusBusy();
< void profileMemTfawBusy();
< void profileMemReadWriteBusy();
< void profileMemDataBusBusy();
< void profileMemRefresh();
< void profileMemRead();
< void profileMemWrite();
< void profileMemWaitCycles(int cycles);
< void profileMemInputQ(int cycles);
< void profileMemBankQ(int cycles);
< void profileMemArbWait(int cycles);
< void profileMemRandBusy();
< void profileMemNotOld();
---
> // return Ruby's start time
> Time getRubyStartTime(){
> return m_ruby_start;
> }
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> // added for MemoryControl:
> void profileMemReq(string name, int bank);
> void profileMemBankBusy(string name);
> void profileMemBusBusy(string name);
> void profileMemTfawBusy(string name);
> void profileMemReadWriteBusy(string name);
> void profileMemDataBusBusy(string name);
> void profileMemRefresh(string name);
> void profileMemRead(string name);
> void profileMemWrite(string name);
> void profileMemWaitCycles(string name, int cycles);
> void profileMemInputQ(string name, int cycles);
> void profileMemBankQ(string name, int cycles);
> void profileMemArbWait(string name, int cycles);
> void profileMemRandBusy(string name);
> void profileMemNotOld(string name);
> //added by SS
> bool getHotLines() { return m_hot_lines; }
> bool getAllInstructions() { return m_all_instructions; }
>
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< // Private Methods
< void addL2StatSample(GenericRequestType requestType, AccessModeType type,
< int msgSize, PrefetchBit pfBit, NodeID id);
< void addL1DStatSample(const CacheMsg& msg, NodeID id);
< void addL1IStatSample(const CacheMsg& msg, NodeID id);
---
> //added by SS
> vector<string> m_memory_control_names;
> // Private Methods
> void addL2StatSample(GenericRequestType requestType, AccessModeType type, int msgSize, PrefetchBit pfBit, NodeID id);
> void addL1DStatSample(const CacheMsg& msg, NodeID id);
> void addL1IStatSample(const CacheMsg& msg, NodeID id);
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< GenericRequestType CacheRequestType_to_GenericRequestType(const CacheRequestType& type);
---
> GenericRequestType CacheRequestType_to_GenericRequestType(const CacheRequestType& type);
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< // Private copy constructor and assignment operator
< Profiler(const Profiler& obj);
< Profiler& operator=(const Profiler& obj);
---
> // Private copy constructor and assignment operator
> Profiler(const Profiler& obj);
> Profiler& operator=(const Profiler& obj);
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< // Data Members (m_ prefix)
< CacheProfiler* m_L1D_cache_profiler_ptr;
< CacheProfiler* m_L1I_cache_profiler_ptr;
< CacheProfiler* m_L2_cache_profiler_ptr;
< AddressProfiler* m_address_profiler_ptr;
< AddressProfiler* m_inst_profiler_ptr;
---
> // Data Members (m_ prefix)
> CacheProfiler* m_L1D_cache_profiler_ptr;
> CacheProfiler* m_L1I_cache_profiler_ptr;
> CacheProfiler* m_L2_cache_profiler_ptr;
> AddressProfiler* m_address_profiler_ptr;
> AddressProfiler* m_inst_profiler_ptr;
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< Vector<int64> m_instructions_executed_at_start;
< Vector<int64> m_cycles_executed_at_start;
---
> Vector<int64> m_instructions_executed_at_start;
> Vector<int64> m_cycles_executed_at_start;
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< ostream* m_periodic_output_file_ptr;
< integer_t m_stats_period;
---
> ostream* m_periodic_output_file_ptr;
> integer_t m_stats_period;
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< Time m_ruby_start;
< time_t m_real_time_start_time;
---
> Time m_ruby_start;
> time_t m_real_time_start_time;
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< int m_num_BA_unicasts;
< int m_num_BA_broadcasts;
---
> int m_num_BA_unicasts;
> int m_num_BA_broadcasts;
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< Vector<integer_t> m_perProcTotalMisses;
< Vector<integer_t> m_perProcUserMisses;
< Vector<integer_t> m_perProcSupervisorMisses;
< Vector<integer_t> m_perProcStartTransaction;
< Vector<integer_t> m_perProcEndTransaction;
< Vector < Vector < integer_t > > m_busyControllerCount;
< integer_t m_busyBankCount;
< Histogram m_multicast_retry_histogram;
---
> Vector<integer_t> m_perProcTotalMisses;
> Vector<integer_t> m_perProcUserMisses;
> Vector<integer_t> m_perProcSupervisorMisses;
> Vector<integer_t> m_perProcStartTransaction;
> Vector<integer_t> m_perProcEndTransaction;
> Vector < Vector < integer_t > > m_busyControllerCount;
> integer_t m_busyBankCount;
> Histogram m_multicast_retry_histogram;
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< Histogram m_L1tbeProfile;
< Histogram m_L2tbeProfile;
< Histogram m_stopTableProfile;
---
> Histogram m_L1tbeProfile;
> Histogram m_L2tbeProfile;
> Histogram m_stopTableProfile;
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< Histogram m_filter_action_histogram;
< Histogram m_tbeProfile;
---
> Histogram m_filter_action_histogram;
> Histogram m_tbeProfile;
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< Histogram m_sequencer_requests;
< Histogram m_store_buffer_size;
< Histogram m_store_buffer_blocks;
< Histogram m_read_sharing_histogram;
< Histogram m_write_sharing_histogram;
< Histogram m_all_sharing_histogram;
< int64 m_cache_to_cache;
< int64 m_memory_to_cache;
---
> Histogram m_sequencer_requests;
> Histogram m_store_buffer_size;
> Histogram m_store_buffer_blocks;
> Histogram m_read_sharing_histogram;
> Histogram m_write_sharing_histogram;
> Histogram m_all_sharing_histogram;
> int64 m_cache_to_cache;
> int64 m_memory_to_cache;
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< Histogram m_prefetchWaitHistogram;
---
> Histogram m_prefetchWaitHistogram;
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< Vector<Histogram> m_missLatencyHistograms;
< Vector<Histogram> m_machLatencyHistograms;
< Histogram m_L2MissLatencyHistogram;
< Histogram m_allMissLatencyHistogram;
---
> Vector<Histogram> m_missLatencyHistograms;
> Vector<Histogram> m_machLatencyHistograms;
> Histogram m_L2MissLatencyHistogram;
> Histogram m_allMissLatencyHistogram;
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< Histogram m_allSWPrefetchLatencyHistogram;
< Histogram m_SWPrefetchL2MissLatencyHistogram;
< Vector<Histogram> m_SWPrefetchLatencyHistograms;
< Vector<Histogram> m_SWPrefetchMachLatencyHistograms;
---
> Histogram m_allSWPrefetchLatencyHistogram;
> Histogram m_SWPrefetchL2MissLatencyHistogram;
> Vector<Histogram> m_SWPrefetchLatencyHistograms;
> Vector<Histogram> m_SWPrefetchMachLatencyHistograms;
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< Histogram m_delayedCyclesHistogram;
< Histogram m_delayedCyclesNonPFHistogram;
< Vector<Histogram> m_delayedCyclesVCHistograms;
---
> Histogram m_delayedCyclesHistogram;
> Histogram m_delayedCyclesNonPFHistogram;
> Vector<Histogram> m_delayedCyclesVCHistograms;
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< int m_predictions;
< int m_predictionOpportunities;
< int m_goodPredictions;
---
> int m_predictions;
> int m_predictionOpportunities;
> int m_goodPredictions;
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< Histogram m_gets_mask_prediction;
< Histogram m_getx_mask_prediction;
< Histogram m_explicit_training_mask;
---
> Histogram m_gets_mask_prediction;
> Histogram m_getx_mask_prediction;
> Histogram m_explicit_training_mask;
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< // For profiling possibly conflicting requests
< Map<Address, Time>* m_conflicting_map_ptr;
< Histogram m_conflicting_histogram;
---
> // For profiling possibly conflicting requests
> Map<Address, Time>* m_conflicting_map_ptr;
> Histogram m_conflicting_histogram;
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< Histogram m_outstanding_requests;
< Histogram m_outstanding_persistent_requests;
---
> Histogram m_outstanding_requests;
> Histogram m_outstanding_persistent_requests;
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< Histogram m_average_latency_estimate;
---
> Histogram m_average_latency_estimate;
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< Map<Address, int>* m_watch_address_list_ptr;
< // counts all initiated cache request including PUTs
< int m_requests;
< Map <string, int>* m_requestProfileMap_ptr;
---
> Map<Address, int>* m_watch_address_list_ptr;
> // counts all initiated cache request including PUTs
> int m_requests;
> Map <string, int>* m_requestProfileMap_ptr;
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< // added for MemoryControl:
< long long int m_memReq;
< long long int m_memBankBusy;
< long long int m_memBusBusy;
< long long int m_memTfawBusy;
< long long int m_memReadWriteBusy;
< long long int m_memDataBusBusy;
< long long int m_memRefresh;
< long long int m_memRead;
< long long int m_memWrite;
< long long int m_memWaitCycles;
< long long int m_memInputQ;
< long long int m_memBankQ;
< long long int m_memArbWait;
< long long int m_memRandBusy;
< long long int m_memNotOld;
< Vector<long long int> m_memBankCount;
---
> // added for MemoryControl:
> //added by SS
> map< string, memory_control_profiler* > m_memory_control_profilers;
303a307,311
> //added by SS
> bool m_hot_lines;
> bool m_all_instructions;
> string m_name;
>
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< obj.print(out);
< out << flush;
< return out;
---
> obj.print(out);
> out << flush;
> return out;