1/* 2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29/* 30 This file has been modified by Kevin Moore and Dan Nussbaum of the 31 Scalable Systems Research Group at Sun Microsystems Laboratories 32 (http://research.sun.com/scalable/) to support the Adaptive 33 Transactional Memory Test Platform (ATMTP). 34 35 Please send email to atmtp-interest@sun.com with feedback, questions, or 36 to request future announcements about ATMTP. 37 38 ---------------------------------------------------------------------- 39 40 File modification date: 2008-02-23 41 42 ---------------------------------------------------------------------- 43*/ 44 45#ifndef __MEM_RUBY_PROFILER_PROFILER_HH__ 46#define __MEM_RUBY_PROFILER_PROFILER_HH__ 47 48#include <iostream> 49#include <map> 50#include <string> 51#include <vector> 52 53#include "base/hashmap.hh" 54#include "mem/protocol/AccessModeType.hh" 55#include "mem/protocol/AccessType.hh" 56#include "mem/protocol/CacheRequestType.hh" 57#include "mem/protocol/GenericMachineType.hh" 58#include "mem/protocol/GenericRequestType.hh" 59#include "mem/protocol/PrefetchBit.hh" 60#include "mem/ruby/common/Address.hh" 61#include "mem/ruby/common/Consumer.hh" 62#include "mem/ruby/common/Global.hh" 63#include "mem/ruby/common/Histogram.hh" 64#include "mem/ruby/common/Set.hh" 65#include "mem/ruby/libruby.hh" 66#include "mem/ruby/system/MachineID.hh" 67#include "mem/ruby/system/MemoryControl.hh" 68#include "mem/ruby/system/NodeID.hh" 69#include "params/RubyProfiler.hh" 70#include "sim/sim_object.hh" 71 72class CacheMsg; 73class AddressProfiler; 74 75class Profiler : public SimObject, public Consumer 76{ 77 public: 78 typedef RubyProfilerParams Params; 79 Profiler(const Params *); 80 ~Profiler(); 81 82 void wakeup(); 83 84 void setPeriodicStatsFile(const std::string& filename); 85 void setPeriodicStatsInterval(integer_t period); 86 87 void printStats(std::ostream& out, bool short_stats=false); 88 void printShortStats(std::ostream& out) { printStats(out, true); } 89 void printTraceStats(std::ostream& out) const; 90 void clearStats(); 91 void printConfig(std::ostream& out) const; 92 void printResourceUsage(std::ostream& out) const; 93 94 AddressProfiler* getAddressProfiler() { return m_address_profiler_ptr; } 95 AddressProfiler* getInstructionProfiler() { return m_inst_profiler_ptr; } 96 97 void addAddressTraceSample(const CacheMsg& msg, NodeID id); 98 99 void profileRequest(const std::string& requestStr); 100 void profileSharing(const Address& addr, AccessType type, 101 NodeID requestor, const Set& sharers, 102 const Set& owner); 103 104 void profileMulticastRetry(const Address& addr, int count); 105 106 void profileFilterAction(int action); 107 108 void profileConflictingRequests(const Address& addr); 109 110 void 111 profileOutstandingRequest(int outstanding) 112 { 113 m_outstanding_requests.add(outstanding); 114 } 115 116 void 117 profileOutstandingPersistentRequest(int outstanding) 118 { 119 m_outstanding_persistent_requests.add(outstanding); 120 } 121 122 void 123 profileAverageLatencyEstimate(int latency) 124 { 125 m_average_latency_estimate.add(latency); 126 } 127 128 void recordPrediction(bool wasGood, bool wasPredicted); 129 130 void startTransaction(int cpu); 131 void endTransaction(int cpu); 132 void profilePFWait(Time waitTime); 133 134 void controllerBusy(MachineID machID); 135 void bankBusy(); 136 137 void missLatency(Time t, 138 RubyRequestType type, 139 const GenericMachineType respondingMach); 140
| 1/* 2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29/* 30 This file has been modified by Kevin Moore and Dan Nussbaum of the 31 Scalable Systems Research Group at Sun Microsystems Laboratories 32 (http://research.sun.com/scalable/) to support the Adaptive 33 Transactional Memory Test Platform (ATMTP). 34 35 Please send email to atmtp-interest@sun.com with feedback, questions, or 36 to request future announcements about ATMTP. 37 38 ---------------------------------------------------------------------- 39 40 File modification date: 2008-02-23 41 42 ---------------------------------------------------------------------- 43*/ 44 45#ifndef __MEM_RUBY_PROFILER_PROFILER_HH__ 46#define __MEM_RUBY_PROFILER_PROFILER_HH__ 47 48#include <iostream> 49#include <map> 50#include <string> 51#include <vector> 52 53#include "base/hashmap.hh" 54#include "mem/protocol/AccessModeType.hh" 55#include "mem/protocol/AccessType.hh" 56#include "mem/protocol/CacheRequestType.hh" 57#include "mem/protocol/GenericMachineType.hh" 58#include "mem/protocol/GenericRequestType.hh" 59#include "mem/protocol/PrefetchBit.hh" 60#include "mem/ruby/common/Address.hh" 61#include "mem/ruby/common/Consumer.hh" 62#include "mem/ruby/common/Global.hh" 63#include "mem/ruby/common/Histogram.hh" 64#include "mem/ruby/common/Set.hh" 65#include "mem/ruby/libruby.hh" 66#include "mem/ruby/system/MachineID.hh" 67#include "mem/ruby/system/MemoryControl.hh" 68#include "mem/ruby/system/NodeID.hh" 69#include "params/RubyProfiler.hh" 70#include "sim/sim_object.hh" 71 72class CacheMsg; 73class AddressProfiler; 74 75class Profiler : public SimObject, public Consumer 76{ 77 public: 78 typedef RubyProfilerParams Params; 79 Profiler(const Params *); 80 ~Profiler(); 81 82 void wakeup(); 83 84 void setPeriodicStatsFile(const std::string& filename); 85 void setPeriodicStatsInterval(integer_t period); 86 87 void printStats(std::ostream& out, bool short_stats=false); 88 void printShortStats(std::ostream& out) { printStats(out, true); } 89 void printTraceStats(std::ostream& out) const; 90 void clearStats(); 91 void printConfig(std::ostream& out) const; 92 void printResourceUsage(std::ostream& out) const; 93 94 AddressProfiler* getAddressProfiler() { return m_address_profiler_ptr; } 95 AddressProfiler* getInstructionProfiler() { return m_inst_profiler_ptr; } 96 97 void addAddressTraceSample(const CacheMsg& msg, NodeID id); 98 99 void profileRequest(const std::string& requestStr); 100 void profileSharing(const Address& addr, AccessType type, 101 NodeID requestor, const Set& sharers, 102 const Set& owner); 103 104 void profileMulticastRetry(const Address& addr, int count); 105 106 void profileFilterAction(int action); 107 108 void profileConflictingRequests(const Address& addr); 109 110 void 111 profileOutstandingRequest(int outstanding) 112 { 113 m_outstanding_requests.add(outstanding); 114 } 115 116 void 117 profileOutstandingPersistentRequest(int outstanding) 118 { 119 m_outstanding_persistent_requests.add(outstanding); 120 } 121 122 void 123 profileAverageLatencyEstimate(int latency) 124 { 125 m_average_latency_estimate.add(latency); 126 } 127 128 void recordPrediction(bool wasGood, bool wasPredicted); 129 130 void startTransaction(int cpu); 131 void endTransaction(int cpu); 132 void profilePFWait(Time waitTime); 133 134 void controllerBusy(MachineID machID); 135 void bankBusy(); 136 137 void missLatency(Time t, 138 RubyRequestType type, 139 const GenericMachineType respondingMach); 140
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141 void swPrefetchLatency(Time t, 142 CacheRequestType type, 143 const GenericMachineType respondingMach); 144 145 void sequencerRequests(int num) { m_sequencer_requests.add(num); } 146 147 void profileTransition(const std::string& component, NodeID version, 148 Address addr, const std::string& state, const std::string& event, 149 const std::string& next_state, const std::string& note); 150 void profileMsgDelay(int virtualNetwork, int delayCycles); 151 152 void print(std::ostream& out) const; 153 154 void rubyWatch(int proc); 155 bool watchAddress(Address addr); 156 157 // return Ruby's start time 158 Time 159 getRubyStartTime() 160 { 161 return m_ruby_start; 162 } 163 164 // added by SS 165 bool getHotLines() { return m_hot_lines; } 166 bool getAllInstructions() { return m_all_instructions; } 167 168 private: 169 // Private copy constructor and assignment operator 170 Profiler(const Profiler& obj); 171 Profiler& operator=(const Profiler& obj); 172 173 AddressProfiler* m_address_profiler_ptr; 174 AddressProfiler* m_inst_profiler_ptr; 175 176 std::vector<int64> m_instructions_executed_at_start; 177 std::vector<int64> m_cycles_executed_at_start; 178 179 std::ostream* m_periodic_output_file_ptr; 180 integer_t m_stats_period; 181 182 Time m_ruby_start; 183 time_t m_real_time_start_time; 184 185 std::vector<std::vector<integer_t> > m_busyControllerCount; 186 integer_t m_busyBankCount; 187 Histogram m_multicast_retry_histogram; 188 189 Histogram m_filter_action_histogram; 190 Histogram m_tbeProfile; 191 192 Histogram m_sequencer_requests; 193 Histogram m_read_sharing_histogram; 194 Histogram m_write_sharing_histogram; 195 Histogram m_all_sharing_histogram; 196 int64 m_cache_to_cache; 197 int64 m_memory_to_cache; 198 199 Histogram m_prefetchWaitHistogram; 200 201 std::vector<Histogram> m_missLatencyHistograms; 202 std::vector<Histogram> m_machLatencyHistograms;
| 153 void swPrefetchLatency(Time t, 154 CacheRequestType type, 155 const GenericMachineType respondingMach); 156 157 void sequencerRequests(int num) { m_sequencer_requests.add(num); } 158 159 void profileTransition(const std::string& component, NodeID version, 160 Address addr, const std::string& state, const std::string& event, 161 const std::string& next_state, const std::string& note); 162 void profileMsgDelay(int virtualNetwork, int delayCycles); 163 164 void print(std::ostream& out) const; 165 166 void rubyWatch(int proc); 167 bool watchAddress(Address addr); 168 169 // return Ruby's start time 170 Time 171 getRubyStartTime() 172 { 173 return m_ruby_start; 174 } 175 176 // added by SS 177 bool getHotLines() { return m_hot_lines; } 178 bool getAllInstructions() { return m_all_instructions; } 179 180 private: 181 // Private copy constructor and assignment operator 182 Profiler(const Profiler& obj); 183 Profiler& operator=(const Profiler& obj); 184 185 AddressProfiler* m_address_profiler_ptr; 186 AddressProfiler* m_inst_profiler_ptr; 187 188 std::vector<int64> m_instructions_executed_at_start; 189 std::vector<int64> m_cycles_executed_at_start; 190 191 std::ostream* m_periodic_output_file_ptr; 192 integer_t m_stats_period; 193 194 Time m_ruby_start; 195 time_t m_real_time_start_time; 196 197 std::vector<std::vector<integer_t> > m_busyControllerCount; 198 integer_t m_busyBankCount; 199 Histogram m_multicast_retry_histogram; 200 201 Histogram m_filter_action_histogram; 202 Histogram m_tbeProfile; 203 204 Histogram m_sequencer_requests; 205 Histogram m_read_sharing_histogram; 206 Histogram m_write_sharing_histogram; 207 Histogram m_all_sharing_histogram; 208 int64 m_cache_to_cache; 209 int64 m_memory_to_cache; 210 211 Histogram m_prefetchWaitHistogram; 212 213 std::vector<Histogram> m_missLatencyHistograms; 214 std::vector<Histogram> m_machLatencyHistograms;
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