1/* 2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29/* 30 This file has been modified by Kevin Moore and Dan Nussbaum of the 31 Scalable Systems Research Group at Sun Microsystems Laboratories 32 (http://research.sun.com/scalable/) to support the Adaptive 33 Transactional Memory Test Platform (ATMTP). 34 35 Please send email to atmtp-interest@sun.com with feedback, questions, or 36 to request future announcements about ATMTP. 37 38 ---------------------------------------------------------------------- 39 40 File modification date: 2008-02-23 41 42 ---------------------------------------------------------------------- 43*/ 44
| 1/* 2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29/* 30 This file has been modified by Kevin Moore and Dan Nussbaum of the 31 Scalable Systems Research Group at Sun Microsystems Laboratories 32 (http://research.sun.com/scalable/) to support the Adaptive 33 Transactional Memory Test Platform (ATMTP). 34 35 Please send email to atmtp-interest@sun.com with feedback, questions, or 36 to request future announcements about ATMTP. 37 38 ---------------------------------------------------------------------- 39 40 File modification date: 2008-02-23 41 42 ---------------------------------------------------------------------- 43*/ 44
|
45/* 46 * Profiler.hh 47 * 48 * Description: 49 * 50 * $Id$ 51 * 52 */
| 45#ifndef __MEM_RUBY_PROFILER_PROFILER_HH__ 46#define __MEM_RUBY_PROFILER_PROFILER_HH__
|
53
| 47
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54#ifndef PROFILER_H 55#define PROFILER_H 56 57#include "mem/ruby/libruby.hh" 58 59#include "mem/ruby/common/Global.hh" 60#include "mem/protocol/GenericMachineType.hh" 61#include "mem/ruby/common/Histogram.hh" 62#include "mem/ruby/common/Consumer.hh"
| |
63#include "mem/protocol/AccessModeType.hh" 64#include "mem/protocol/AccessType.hh"
| 48#include "mem/protocol/AccessModeType.hh" 49#include "mem/protocol/AccessType.hh"
|
65#include "mem/ruby/system/NodeID.hh" 66#include "mem/ruby/system/MachineID.hh"
| 50#include "mem/protocol/CacheRequestType.hh" 51#include "mem/protocol/GenericMachineType.hh" 52#include "mem/protocol/GenericRequestType.hh"
|
67#include "mem/protocol/PrefetchBit.hh" 68#include "mem/ruby/common/Address.hh"
| 53#include "mem/protocol/PrefetchBit.hh" 54#include "mem/ruby/common/Address.hh"
|
| 55#include "mem/ruby/common/Consumer.hh" 56#include "mem/ruby/common/Global.hh" 57#include "mem/ruby/common/Histogram.hh"
|
69#include "mem/ruby/common/Set.hh"
| 58#include "mem/ruby/common/Set.hh"
|
70#include "mem/protocol/CacheRequestType.hh" 71#include "mem/protocol/GenericRequestType.hh"
| 59#include "mem/ruby/libruby.hh" 60#include "mem/ruby/system/MachineID.hh"
|
72#include "mem/ruby/system/MemoryControl.hh"
| 61#include "mem/ruby/system/MemoryControl.hh"
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73
| 62#include "mem/ruby/system/NodeID.hh"
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74#include "params/RubyProfiler.hh" 75#include "sim/sim_object.hh" 76 77class CacheMsg; 78class AddressProfiler; 79 80template <class KEY_TYPE, class VALUE_TYPE> class Map; 81
| 63#include "params/RubyProfiler.hh" 64#include "sim/sim_object.hh" 65 66class CacheMsg; 67class AddressProfiler; 68 69template <class KEY_TYPE, class VALUE_TYPE> class Map; 70
|
82class Profiler : public SimObject, public Consumer { 83public: 84 // Constructors
| 71class Profiler : public SimObject, public Consumer 72{ 73 public:
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85 typedef RubyProfilerParams Params;
| 74 typedef RubyProfilerParams Params;
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86 Profiler(const Params *);
| 75 Profiler(const Params *); 76 ~Profiler();
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87
| 77
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88 // Destructor 89 ~Profiler();
| 78 void wakeup();
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90
| 79
|
91 // Public Methods 92 void wakeup();
| 80 void setPeriodicStatsFile(const string& filename); 81 void setPeriodicStatsInterval(integer_t period);
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93
| 82
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94 void setPeriodicStatsFile(const string& filename); 95 void setPeriodicStatsInterval(integer_t period);
| 83 void printStats(ostream& out, bool short_stats=false); 84 void printShortStats(ostream& out) { printStats(out, true); } 85 void printTraceStats(ostream& out) const; 86 void clearStats(); 87 void printConfig(ostream& out) const; 88 void printResourceUsage(ostream& out) const;
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96
| 89
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97 void printStats(ostream& out, bool short_stats=false); 98 void printShortStats(ostream& out) { printStats(out, true); } 99 void printTraceStats(ostream& out) const; 100 void clearStats(); 101 void printConfig(ostream& out) const; 102 void printResourceUsage(ostream& out) const;
| 90 AddressProfiler* getAddressProfiler() { return m_address_profiler_ptr; } 91 AddressProfiler* getInstructionProfiler() { return m_inst_profiler_ptr; }
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103
| 92
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104 AddressProfiler* getAddressProfiler() { return m_address_profiler_ptr; } 105 AddressProfiler* getInstructionProfiler() { return m_inst_profiler_ptr; }
| 93 void addAddressTraceSample(const CacheMsg& msg, NodeID id);
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106
| 94
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107 void addAddressTraceSample(const CacheMsg& msg, NodeID id);
| 95 void profileRequest(const string& requestStr); 96 void profileSharing(const Address& addr, AccessType type, 97 NodeID requestor, const Set& sharers, 98 const Set& owner);
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108
| 99
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109 void profileRequest(const string& requestStr); 110 void profileSharing(const Address& addr, AccessType type, NodeID requestor, const Set& sharers, const Set& owner);
| 100 void profileMulticastRetry(const Address& addr, int count);
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111
| 101
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112 void profileMulticastRetry(const Address& addr, int count);
| 102 void profileFilterAction(int action);
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113
| 103
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114 void profileFilterAction(int action);
| 104 void profileConflictingRequests(const Address& addr);
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115
| 105
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116 void profileConflictingRequests(const Address& addr); 117 void profileOutstandingRequest(int outstanding) { m_outstanding_requests.add(outstanding); } 118 void profileOutstandingPersistentRequest(int outstanding) { m_outstanding_persistent_requests.add(outstanding); } 119 void profileAverageLatencyEstimate(int latency) { m_average_latency_estimate.add(latency); }
| 106 void 107 profileOutstandingRequest(int outstanding) 108 { 109 m_outstanding_requests.add(outstanding); 110 }
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120
| 111
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121 void recordPrediction(bool wasGood, bool wasPredicted);
| 112 void 113 profileOutstandingPersistentRequest(int outstanding) 114 { 115 m_outstanding_persistent_requests.add(outstanding); 116 }
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122
| 117
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123 void startTransaction(int cpu); 124 void endTransaction(int cpu); 125 void profilePFWait(Time waitTime);
| 118 void 119 profileAverageLatencyEstimate(int latency) 120 { 121 m_average_latency_estimate.add(latency); 122 }
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126
| 123
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127 void controllerBusy(MachineID machID); 128 void bankBusy(); 129 void missLatency(Time t, RubyRequestType type); 130 void swPrefetchLatency(Time t, CacheRequestType type, GenericMachineType respondingMach); 131 void sequencerRequests(int num) { m_sequencer_requests.add(num); }
| 124 void recordPrediction(bool wasGood, bool wasPredicted);
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132
| 125
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133 void profileTransition(const string& component, NodeID version, Address addr, 134 const string& state, const string& event, 135 const string& next_state, const string& note); 136 void profileMsgDelay(int virtualNetwork, int delayCycles);
| 126 void startTransaction(int cpu); 127 void endTransaction(int cpu); 128 void profilePFWait(Time waitTime);
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137
| 129
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138 void print(ostream& out) const;
| 130 void controllerBusy(MachineID machID); 131 void bankBusy(); 132 void missLatency(Time t, RubyRequestType type); 133 void swPrefetchLatency(Time t, CacheRequestType type, 134 GenericMachineType respondingMach); 135 void sequencerRequests(int num) { m_sequencer_requests.add(num); }
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139
| 136
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140 void rubyWatch(int proc); 141 bool watchAddress(Address addr);
| 137 void profileTransition(const string& component, NodeID version, 138 Address addr, const string& state, 139 const string& event, const string& next_state, 140 const string& note); 141 void profileMsgDelay(int virtualNetwork, int delayCycles);
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142
| 142
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143 // return Ruby's start time 144 Time getRubyStartTime(){ 145 return m_ruby_start; 146 }
| 143 void print(ostream& out) const;
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147
| 144
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148 //added by SS 149 bool getHotLines() { return m_hot_lines; } 150 bool getAllInstructions() { return m_all_instructions; }
| 145 void rubyWatch(int proc); 146 bool watchAddress(Address addr);
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151
| 147
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152private:
| 148 // return Ruby's start time 149 Time 150 getRubyStartTime() 151 { 152 return m_ruby_start; 153 }
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153
| 154
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154 // Private copy constructor and assignment operator 155 Profiler(const Profiler& obj); 156 Profiler& operator=(const Profiler& obj);
| 155 // added by SS 156 bool getHotLines() { return m_hot_lines; } 157 bool getAllInstructions() { return m_all_instructions; }
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157
| 158
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158 // Data Members (m_ prefix) 159 AddressProfiler* m_address_profiler_ptr; 160 AddressProfiler* m_inst_profiler_ptr;
| 159 private: 160 // Private copy constructor and assignment operator 161 Profiler(const Profiler& obj); 162 Profiler& operator=(const Profiler& obj);
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161
| 163
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162 Vector<int64> m_instructions_executed_at_start; 163 Vector<int64> m_cycles_executed_at_start;
| 164 AddressProfiler* m_address_profiler_ptr; 165 AddressProfiler* m_inst_profiler_ptr;
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164
| 166
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165 ostream* m_periodic_output_file_ptr; 166 integer_t m_stats_period;
| 167 Vector<int64> m_instructions_executed_at_start; 168 Vector<int64> m_cycles_executed_at_start;
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167
| 169
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168 Time m_ruby_start; 169 time_t m_real_time_start_time;
| 170 ostream* m_periodic_output_file_ptr; 171 integer_t m_stats_period;
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170
| 172
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171 Vector < Vector < integer_t > > m_busyControllerCount; 172 integer_t m_busyBankCount; 173 Histogram m_multicast_retry_histogram;
| 173 Time m_ruby_start; 174 time_t m_real_time_start_time;
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174
| 175
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175 Histogram m_filter_action_histogram; 176 Histogram m_tbeProfile;
| 176 Vector <Vector<integer_t> > m_busyControllerCount; 177 integer_t m_busyBankCount; 178 Histogram m_multicast_retry_histogram;
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177
| 179
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178 Histogram m_sequencer_requests; 179 Histogram m_read_sharing_histogram; 180 Histogram m_write_sharing_histogram; 181 Histogram m_all_sharing_histogram; 182 int64 m_cache_to_cache; 183 int64 m_memory_to_cache;
| 180 Histogram m_filter_action_histogram; 181 Histogram m_tbeProfile;
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184
| 182
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185 Histogram m_prefetchWaitHistogram;
| 183 Histogram m_sequencer_requests; 184 Histogram m_read_sharing_histogram; 185 Histogram m_write_sharing_histogram; 186 Histogram m_all_sharing_histogram; 187 int64 m_cache_to_cache; 188 int64 m_memory_to_cache;
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186
| 189
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187 Vector<Histogram> m_missLatencyHistograms; 188 Vector<Histogram> m_machLatencyHistograms; 189 Histogram m_allMissLatencyHistogram;
| 190 Histogram m_prefetchWaitHistogram;
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190
| 191
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191 Histogram m_allSWPrefetchLatencyHistogram; 192 Histogram m_SWPrefetchL2MissLatencyHistogram; 193 Vector<Histogram> m_SWPrefetchLatencyHistograms; 194 Vector<Histogram> m_SWPrefetchMachLatencyHistograms;
| 192 Vector<Histogram> m_missLatencyHistograms; 193 Vector<Histogram> m_machLatencyHistograms; 194 Histogram m_allMissLatencyHistogram;
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195
| 195
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196 Histogram m_delayedCyclesHistogram; 197 Histogram m_delayedCyclesNonPFHistogram; 198 Vector<Histogram> m_delayedCyclesVCHistograms;
| 196 Histogram m_allSWPrefetchLatencyHistogram; 197 Histogram m_SWPrefetchL2MissLatencyHistogram; 198 Vector<Histogram> m_SWPrefetchLatencyHistograms; 199 Vector<Histogram> m_SWPrefetchMachLatencyHistograms;
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199
| 200
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200 Histogram m_outstanding_requests; 201 Histogram m_outstanding_persistent_requests;
| 201 Histogram m_delayedCyclesHistogram; 202 Histogram m_delayedCyclesNonPFHistogram; 203 Vector<Histogram> m_delayedCyclesVCHistograms;
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202
| 204
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203 Histogram m_average_latency_estimate;
| 205 Histogram m_outstanding_requests; 206 Histogram m_outstanding_persistent_requests;
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204
| 207
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205 Map<Address, int>* m_watch_address_list_ptr; 206 // counts all initiated cache request including PUTs 207 int m_requests; 208 Map <string, int>* m_requestProfileMap_ptr;
| 208 Histogram m_average_latency_estimate;
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209
| 209
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210 //added by SS 211 bool m_hot_lines; 212 bool m_all_instructions;
| 210 Map<Address, int>* m_watch_address_list_ptr; 211 // counts all initiated cache request including PUTs 212 int m_requests; 213 Map <string, int>* m_requestProfileMap_ptr;
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213
| 214
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214 int m_num_of_sequencers;
| 215 //added by SS 216 bool m_hot_lines; 217 bool m_all_instructions; 218 219 int m_num_of_sequencers;
|
215}; 216
| 220}; 221
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217// Output operator declaration 218ostream& operator<<(ostream& out, const Profiler& obj); 219 220// ******************* Definitions ******************* 221 222// Output operator definition 223extern inline 224ostream& operator<<(ostream& out, const Profiler& obj)
| 222inline ostream& 223operator<<(ostream& out, const Profiler& obj)
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225{
| 224{
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226 obj.print(out); 227 out << flush; 228 return out;
| 225 obj.print(out); 226 out << flush; 227 return out;
|
229} 230
| 228} 229
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231#endif //PROFILER_H
| 230#endif // __MEM_RUBY_PROFILER_PROFILER_HH__
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232 233
| 231 232
|