1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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133
134 void controllerBusy(MachineID machID);
135 void bankBusy();
136
137 void missLatency(Time t,
138 RubyRequestType type,
139 const GenericMachineType respondingMach);
140
141 void swPrefetchLatency(Time t,
142 CacheRequestType type,
143 const GenericMachineType respondingMach);
144
145 void sequencerRequests(int num) { m_sequencer_requests.add(num); }
146
147 void profileTransition(const std::string& component, NodeID version,
148 Address addr, const std::string& state, const std::string& event,

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195 Histogram m_all_sharing_histogram;
196 int64 m_cache_to_cache;
197 int64 m_memory_to_cache;
198
199 Histogram m_prefetchWaitHistogram;
200
201 std::vector<Histogram> m_missLatencyHistograms;
202 std::vector<Histogram> m_machLatencyHistograms;
203 Histogram m_allMissLatencyHistogram;
204
205 Histogram m_allSWPrefetchLatencyHistogram;
206 Histogram m_SWPrefetchL2MissLatencyHistogram;
207 std::vector<Histogram> m_SWPrefetchLatencyHistograms;
208 std::vector<Histogram> m_SWPrefetchMachLatencyHistograms;
209
210 Histogram m_delayedCyclesHistogram;

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