1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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67#include "mem/protocol/PrefetchBit.hh"
68#include "mem/ruby/common/Address.hh"
69#include "mem/ruby/common/Set.hh"
70#include "mem/protocol/CacheRequestType.hh"
71#include "mem/protocol/GenericRequestType.hh"
72#include "mem/ruby/system/MemoryControl.hh"
73
74class CacheMsg;
75class AddressProfiler;
76
77template <class KEY_TYPE, class VALUE_TYPE> class Map;
78
79struct memory_control_profiler {
80 long long int m_memReq;
81 long long int m_memBankBusy;
82 long long int m_memBusBusy;

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134
135 void profileFilterAction(int action);
136
137 void profileConflictingRequests(const Address& addr);
138 void profileOutstandingRequest(int outstanding) { m_outstanding_requests.add(outstanding); }
139 void profileOutstandingPersistentRequest(int outstanding) { m_outstanding_persistent_requests.add(outstanding); }
140 void profileAverageLatencyEstimate(int latency) { m_average_latency_estimate.add(latency); }
141
142 void recordPrediction(bool wasGood, bool wasPredicted);
143
144 void startTransaction(int cpu);
145 void endTransaction(int cpu);
146 void profilePFWait(Time waitTime);
147
148 void controllerBusy(MachineID machID);
149 void bankBusy();
150 void missLatency(Time t, RubyRequestType type);
151 void swPrefetchLatency(Time t, CacheRequestType type, GenericMachineType respondingMach);
152 void sequencerRequests(int num) { m_sequencer_requests.add(num); }
153
154 void profileTransition(const string& component, NodeID version, Address addr,
155 const string& state, const string& event,
156 const string& next_state, const string& note);
157 void profileMsgDelay(int virtualNetwork, int delayCycles);
158
159 void print(ostream& out) const;
160
161 int64 getTotalTransactionsExecuted() const;
162
163 void rubyWatch(int proc);
164 bool watchAddress(Address addr);
165
166 // return Ruby's start time
167 Time getRubyStartTime(){
168 return m_ruby_start;

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192 //added by SS
193 vector<string> m_memory_control_names;
194
195 // Private copy constructor and assignment operator
196 Profiler(const Profiler& obj);
197 Profiler& operator=(const Profiler& obj);
198
199 // Data Members (m_ prefix)
200 AddressProfiler* m_address_profiler_ptr;
201 AddressProfiler* m_inst_profiler_ptr;
202
203 Vector<int64> m_instructions_executed_at_start;
204 Vector<int64> m_cycles_executed_at_start;
205
206 ostream* m_periodic_output_file_ptr;
207 integer_t m_stats_period;
208
209 Time m_ruby_start;
210 time_t m_real_time_start_time;
211
212 Vector<integer_t> m_perProcTotalMisses;
213 Vector<integer_t> m_perProcUserMisses;
214 Vector<integer_t> m_perProcSupervisorMisses;
215 Vector<integer_t> m_perProcStartTransaction;
216 Vector<integer_t> m_perProcEndTransaction;
217 Vector < Vector < integer_t > > m_busyControllerCount;
218 integer_t m_busyBankCount;
219 Histogram m_multicast_retry_histogram;
220
221 Histogram m_filter_action_histogram;
222 Histogram m_tbeProfile;
223
224 Histogram m_sequencer_requests;
225 Histogram m_read_sharing_histogram;
226 Histogram m_write_sharing_histogram;
227 Histogram m_all_sharing_histogram;
228 int64 m_cache_to_cache;
229 int64 m_memory_to_cache;
230
231 Histogram m_prefetchWaitHistogram;
232
233 Vector<Histogram> m_missLatencyHistograms;
234 Vector<Histogram> m_machLatencyHistograms;
235 Histogram m_allMissLatencyHistogram;
236
237 Histogram m_allSWPrefetchLatencyHistogram;
238 Histogram m_SWPrefetchL2MissLatencyHistogram;
239 Vector<Histogram> m_SWPrefetchLatencyHistograms;
240 Vector<Histogram> m_SWPrefetchMachLatencyHistograms;
241
242 Histogram m_delayedCyclesHistogram;
243 Histogram m_delayedCyclesNonPFHistogram;
244 Vector<Histogram> m_delayedCyclesVCHistograms;
245
246 Histogram m_outstanding_requests;
247 Histogram m_outstanding_persistent_requests;
248
249 Histogram m_average_latency_estimate;
250
251 Map<Address, int>* m_watch_address_list_ptr;
252 // counts all initiated cache request including PUTs
253 int m_requests;

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