Profiler.cc (7456:8b9be6e12c9b) | Profiler.cc (7546:84e8f914b3b8) |
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1/* 2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 560 unchanged lines hidden (view full) --- 569void 570Profiler::bankBusy() 571{ 572 m_busyBankCount++; 573} 574 575// non-zero cycle demand request 576void | 1/* 2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 560 unchanged lines hidden (view full) --- 569void 570Profiler::bankBusy() 571{ 572 m_busyBankCount++; 573} 574 575// non-zero cycle demand request 576void |
577Profiler::missLatency(Time t, RubyRequestType type) | 577Profiler::missLatency(Time cycles, 578 RubyRequestType type, 579 const GenericMachineType respondingMach) |
578{ | 580{ |
579 m_allMissLatencyHistogram.add(t); 580 m_missLatencyHistograms[type].add(t); | 581 m_allMissLatencyHistogram.add(cycles); 582 m_missLatencyHistograms[type].add(cycles); 583 m_machLatencyHistograms[respondingMach].add(cycles); |
581} 582 583// non-zero cycle prefetch request 584void | 584} 585 586// non-zero cycle prefetch request 587void |
585Profiler::swPrefetchLatency(Time t, CacheRequestType type, 586 GenericMachineType respondingMach) | 588Profiler::swPrefetchLatency(Time cycles, 589 CacheRequestType type, 590 const GenericMachineType respondingMach) |
587{ | 591{ |
588 m_allSWPrefetchLatencyHistogram.add(t); 589 m_SWPrefetchLatencyHistograms[type].add(t); 590 m_SWPrefetchMachLatencyHistograms[respondingMach].add(t); | 592 m_allSWPrefetchLatencyHistogram.add(cycles); 593 m_SWPrefetchLatencyHistograms[type].add(cycles); 594 m_SWPrefetchMachLatencyHistograms[respondingMach].add(cycles); |
591 if (respondingMach == GenericMachineType_Directory || 592 respondingMach == GenericMachineType_NUM) { | 595 if (respondingMach == GenericMachineType_Directory || 596 respondingMach == GenericMachineType_NUM) { |
593 m_SWPrefetchL2MissLatencyHistogram.add(t); | 597 m_SWPrefetchL2MissLatencyHistogram.add(cycles); |
594 } 595} 596 597void 598Profiler::profileTransition(const string& component, NodeID version, 599 Address addr, const string& state, const string& event, 600 const string& next_state, const string& note) 601{ --- 87 unchanged lines hidden --- | 598 } 599} 600 601void 602Profiler::profileTransition(const string& component, NodeID version, 603 Address addr, const string& state, const string& event, 604 const string& next_state, const string& note) 605{ --- 87 unchanged lines hidden --- |