Profiler.cc (6896:649e40aad897) Profiler.cc (6897:cfeb3d9563dd)
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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85 m_stats_period = 1000000; // Default
86 m_periodic_output_file_ptr = &cerr;
87
88 m_hot_lines = p->hot_lines;
89 m_all_instructions = p->all_instructions;
90
91 m_num_of_sequencers = p->num_of_sequencers;
92
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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85 m_stats_period = 1000000; // Default
86 m_periodic_output_file_ptr = &cerr;
87
88 m_hot_lines = p->hot_lines;
89 m_all_instructions = p->all_instructions;
90
91 m_num_of_sequencers = p->num_of_sequencers;
92
93 //
94 // Initialize the memory controller profiler structs
95 //
96 m_mc_profilers.setSize(p->mem_cntrl_count);
97 for (int mem_cntrl = 0; mem_cntrl < p->mem_cntrl_count; mem_cntrl++) {
98 m_mc_profilers[mem_cntrl] = new memory_control_profiler;
99 m_mc_profilers[mem_cntrl]->m_memReq = 0;
100 m_mc_profilers[mem_cntrl]->m_memBankBusy = 0;
101 m_mc_profilers[mem_cntrl]->m_memBusBusy = 0;
102 m_mc_profilers[mem_cntrl]->m_memReadWriteBusy = 0;
103 m_mc_profilers[mem_cntrl]->m_memDataBusBusy = 0;
104 m_mc_profilers[mem_cntrl]->m_memTfawBusy = 0;
105 m_mc_profilers[mem_cntrl]->m_memRefresh = 0;
106 m_mc_profilers[mem_cntrl]->m_memRead = 0;
107 m_mc_profilers[mem_cntrl]->m_memWrite = 0;
108 m_mc_profilers[mem_cntrl]->m_memWaitCycles = 0;
109 m_mc_profilers[mem_cntrl]->m_memInputQ = 0;
110 m_mc_profilers[mem_cntrl]->m_memBankQ = 0;
111 m_mc_profilers[mem_cntrl]->m_memArbWait = 0;
112 m_mc_profilers[mem_cntrl]->m_memRandBusy = 0;
113 m_mc_profilers[mem_cntrl]->m_memNotOld = 0;
114
115 m_mc_profilers[mem_cntrl]->m_banks_per_rank = p->banks_per_rank;
116 m_mc_profilers[mem_cntrl]->m_ranks_per_dimm = p->ranks_per_dimm;
117 m_mc_profilers[mem_cntrl]->m_dimms_per_channel =
118 p->dimms_per_channel;
119
120 int totalBanks = p->banks_per_rank *
121 p->ranks_per_dimm *
122 p->dimms_per_channel;
123
124 m_mc_profilers[mem_cntrl]->m_memBankCount.setSize(totalBanks);
125 }
126
127 m_hot_lines = false;
128 m_all_instructions = false;
129
130 m_address_profiler_ptr = new AddressProfiler(m_num_of_sequencers);
131 m_address_profiler_ptr -> setHotLines(m_hot_lines);
132 m_address_profiler_ptr -> setAllInstructions(m_all_instructions);
133
134 if (m_all_instructions) {

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139}
140
141Profiler::~Profiler()
142{
143 if (m_periodic_output_file_ptr != &cerr) {
144 delete m_periodic_output_file_ptr;
145 }
146
93 m_hot_lines = false;
94 m_all_instructions = false;
95
96 m_address_profiler_ptr = new AddressProfiler(m_num_of_sequencers);
97 m_address_profiler_ptr -> setHotLines(m_hot_lines);
98 m_address_profiler_ptr -> setAllInstructions(m_all_instructions);
99
100 if (m_all_instructions) {

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105}
106
107Profiler::~Profiler()
108{
109 if (m_periodic_output_file_ptr != &cerr) {
110 delete m_periodic_output_file_ptr;
111 }
112
147 for (int mem_cntrl = 0;
148 mem_cntrl < m_mc_profilers.size();
149 mem_cntrl++) {
150 delete m_mc_profilers[mem_cntrl];
151 }
152
153 delete m_requestProfileMap_ptr;
154}
155
156void Profiler::wakeup()
157{
158 // FIXME - avoid the repeated code
159
160 Vector<integer_t> perProcCycleCount;

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358 out << "transactions_ended: " << transactions_ended << " " << m_perProcEndTransaction << endl;
359 out << "cycles_per_transaction: " << cycles_per_transaction << " " << perProcCyclesPerTrans << endl;
360 out << "misses_per_transaction: " << misses_per_transaction << " " << perProcMissesPerTrans << endl;
361
362 out << endl;
363
364 out << endl;
365
113 delete m_requestProfileMap_ptr;
114}
115
116void Profiler::wakeup()
117{
118 // FIXME - avoid the repeated code
119
120 Vector<integer_t> perProcCycleCount;

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318 out << "transactions_ended: " << transactions_ended << " " << m_perProcEndTransaction << endl;
319 out << "cycles_per_transaction: " << cycles_per_transaction << " " << perProcCyclesPerTrans << endl;
320 out << "misses_per_transaction: " << misses_per_transaction << " " << perProcMissesPerTrans << endl;
321
322 out << endl;
323
324 out << endl;
325
366 for (int mem_cntrl = 0;
367 mem_cntrl < m_mc_profilers.size();
368 mem_cntrl++) {
369 uint64 m_memReq = m_mc_profilers[mem_cntrl]->m_memReq;
370 uint64 m_memRefresh = m_mc_profilers[mem_cntrl]->m_memRefresh;
371 uint64 m_memInputQ = m_mc_profilers[mem_cntrl]->m_memInputQ;
372 uint64 m_memBankQ = m_mc_profilers[mem_cntrl]->m_memBankQ;
373 uint64 m_memWaitCycles = m_mc_profilers[mem_cntrl]->m_memWaitCycles;
374 uint64 m_memRead = m_mc_profilers[mem_cntrl]->m_memRead;
375 uint64 m_memWrite = m_mc_profilers[mem_cntrl]->m_memWrite;
376 uint64 m_memBankBusy = m_mc_profilers[mem_cntrl]->m_memBankBusy;
377 uint64 m_memRandBusy = m_mc_profilers[mem_cntrl]->m_memRandBusy;
378 uint64 m_memNotOld = m_mc_profilers[mem_cntrl]->m_memNotOld;
379 uint64 m_memArbWait = m_mc_profilers[mem_cntrl]->m_memArbWait;
380 uint64 m_memBusBusy = m_mc_profilers[mem_cntrl]->m_memBusBusy;
381 uint64 m_memTfawBusy = m_mc_profilers[mem_cntrl]->m_memTfawBusy;
382 uint64 m_memReadWriteBusy = m_mc_profilers[mem_cntrl]->m_memReadWriteBusy;
383 uint64 m_memDataBusBusy = m_mc_profilers[mem_cntrl]->m_memDataBusBusy;
384 Vector<uint64> m_memBankCount = m_mc_profilers[mem_cntrl]->m_memBankCount;
385
386 if (m_memReq || m_memRefresh) { // if there's a memory controller at all
387 uint64 total_stalls = m_memInputQ + m_memBankQ + m_memWaitCycles;
388 double stallsPerReq = total_stalls * 1.0 / m_memReq;
389 out << "Memory control " << mem_cntrl << ":" << endl;
390 out << " memory_total_requests: " << m_memReq << endl; // does not include refreshes
391 out << " memory_reads: " << m_memRead << endl;
392 out << " memory_writes: " << m_memWrite << endl;
393 out << " memory_refreshes: " << m_memRefresh << endl;
394 out << " memory_total_request_delays: " << total_stalls << endl;
395 out << " memory_delays_per_request: " << stallsPerReq << endl;
396 out << " memory_delays_in_input_queue: " << m_memInputQ << endl;
397 out << " memory_delays_behind_head_of_bank_queue: " << m_memBankQ << endl;
398 out << " memory_delays_stalled_at_head_of_bank_queue: " << m_memWaitCycles << endl;
399 // Note: The following "memory stalls" entries are a breakdown of the
400 // cycles which already showed up in m_memWaitCycles. The order is
401 // significant; it is the priority of attributing the cycles.
402 // For example, bank_busy is before arbitration because if the bank was
403 // busy, we didn't even check arbitration.
404 // Note: "not old enough" means that since we grouped waiting heads-of-queues
405 // into batches to avoid starvation, a request in a newer batch
406 // didn't try to arbitrate yet because there are older requests waiting.
407 out << " memory_stalls_for_bank_busy: " << m_memBankBusy << endl;
408 out << " memory_stalls_for_random_busy: " << m_memRandBusy << endl;
409 out << " memory_stalls_for_anti_starvation: " << m_memNotOld << endl;
410 out << " memory_stalls_for_arbitration: " << m_memArbWait << endl;
411 out << " memory_stalls_for_bus: " << m_memBusBusy << endl;
412 out << " memory_stalls_for_tfaw: " << m_memTfawBusy << endl;
413 out << " memory_stalls_for_read_write_turnaround: " << m_memReadWriteBusy << endl;
414 out << " memory_stalls_for_read_read_turnaround: " << m_memDataBusBusy << endl;
415 out << " accesses_per_bank: ";
416 for (int bank=0; bank < m_memBankCount.size(); bank++) {
417 out << m_memBankCount[bank] << " ";
418 //if ((bank % 8) == 7) out << " " << endl;
419 }
420 out << endl;
421 out << endl;
422 }
423 }
424 if (!short_stats) {
425 out << "Busy Controller Counts:" << endl;
426 for(int i=0; i < MachineType_NUM; i++) {
427 for(int j=0; j < MachineType_base_count((MachineType)i); j++) {
428 MachineID machID;
429 machID.type = (MachineType)i;
430 machID.num = j;
431 out << machID << ":" << m_busyControllerCount[i][j] << " ";

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638 m_requestProfileMap_ptr->clear();
639
640 // count requests profiled
641 m_requests = 0;
642
643 m_outstanding_requests.clear();
644 m_outstanding_persistent_requests.clear();
645
326 if (!short_stats) {
327 out << "Busy Controller Counts:" << endl;
328 for(int i=0; i < MachineType_NUM; i++) {
329 for(int j=0; j < MachineType_base_count((MachineType)i); j++) {
330 MachineID machID;
331 machID.type = (MachineType)i;
332 machID.num = j;
333 out << machID << ":" << m_busyControllerCount[i][j] << " ";

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540 m_requestProfileMap_ptr->clear();
541
542 // count requests profiled
543 m_requests = 0;
544
545 m_outstanding_requests.clear();
546 m_outstanding_persistent_requests.clear();
547
646//added by SS
647 vector<string>::iterator it;
648
649 for (int mem_cntrl = 0;
650 mem_cntrl < m_mc_profilers.size();
651 mem_cntrl++) {
652 m_mc_profilers[mem_cntrl]->m_memReq = 0;
653 m_mc_profilers[mem_cntrl]->m_memBankBusy = 0;
654 m_mc_profilers[mem_cntrl]->m_memBusBusy = 0;
655 m_mc_profilers[mem_cntrl]->m_memTfawBusy = 0;
656 m_mc_profilers[mem_cntrl]->m_memReadWriteBusy = 0;
657 m_mc_profilers[mem_cntrl]->m_memDataBusBusy = 0;
658 m_mc_profilers[mem_cntrl]->m_memRefresh = 0;
659 m_mc_profilers[mem_cntrl]->m_memRead = 0;
660 m_mc_profilers[mem_cntrl]->m_memWrite = 0;
661 m_mc_profilers[mem_cntrl]->m_memWaitCycles = 0;
662 m_mc_profilers[mem_cntrl]->m_memInputQ = 0;
663 m_mc_profilers[mem_cntrl]->m_memBankQ = 0;
664 m_mc_profilers[mem_cntrl]->m_memArbWait = 0;
665 m_mc_profilers[mem_cntrl]->m_memRandBusy = 0;
666 m_mc_profilers[mem_cntrl]->m_memNotOld = 0;
667
668 for (int bank=0;
669 bank < m_mc_profilers[mem_cntrl]->m_memBankCount.size();
670 bank++) {
671 m_mc_profilers[mem_cntrl]->m_memBankCount[bank] = 0;
672 }
673 }
674 // Flush the prefetches through the system - used so that there are no outstanding requests after stats are cleared
675 //g_eventQueue_ptr->triggerAllEvents();
676
677 // update the start time
678 m_ruby_start = g_eventQueue_ptr->getTime();
679}
680
681void Profiler::addAddressTraceSample(const CacheMsg& msg, NodeID id)

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858 else
859 return false;
860}
861
862int64 Profiler::getTotalTransactionsExecuted() const {
863 return m_perProcEndTransaction.sum();
864}
865
548 // Flush the prefetches through the system - used so that there are no outstanding requests after stats are cleared
549 //g_eventQueue_ptr->triggerAllEvents();
550
551 // update the start time
552 m_ruby_start = g_eventQueue_ptr->getTime();
553}
554
555void Profiler::addAddressTraceSample(const CacheMsg& msg, NodeID id)

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732 else
733 return false;
734}
735
736int64 Profiler::getTotalTransactionsExecuted() const {
737 return m_perProcEndTransaction.sum();
738}
739
866// For MemoryControl:
867void Profiler::profileMemReq(int mem_cntrl, int bank) {
868 m_mc_profilers[mem_cntrl]->m_memReq++;
869 m_mc_profilers[mem_cntrl]->m_memBankCount[bank]++;
870}
871
740
872void Profiler::profileMemBankBusy(int mem_cntrl) {
873 m_mc_profilers[mem_cntrl]->m_memBankBusy++;
874}
875
876void Profiler::profileMemBusBusy(int mem_cntrl) {
877 m_mc_profilers[mem_cntrl]->m_memBusBusy++;
878}
879
880void Profiler::profileMemReadWriteBusy(int mem_cntrl) {
881 m_mc_profilers[mem_cntrl]->m_memReadWriteBusy++;
882}
883
884void Profiler::profileMemDataBusBusy(int mem_cntrl) {
885 m_mc_profilers[mem_cntrl]->m_memDataBusBusy++;
886}
887
888void Profiler::profileMemTfawBusy(int mem_cntrl) {
889 m_mc_profilers[mem_cntrl]->m_memTfawBusy++;
890}
891
892void Profiler::profileMemRefresh(int mem_cntrl) {
893 m_mc_profilers[mem_cntrl]->m_memRefresh++;
894}
895
896void Profiler::profileMemRead(int mem_cntrl) {
897 m_mc_profilers[mem_cntrl]->m_memRead++;
898}
899
900void Profiler::profileMemWrite(int mem_cntrl) {
901 m_mc_profilers[mem_cntrl]->m_memWrite++;
902}
903
904void Profiler::profileMemWaitCycles(int mem_cntrl, int cycles) {
905 m_mc_profilers[mem_cntrl]->m_memWaitCycles += cycles;
906}
907
908void Profiler::profileMemInputQ(int mem_cntrl, int cycles) {
909 m_mc_profilers[mem_cntrl]->m_memInputQ += cycles;
910}
911
912void Profiler::profileMemBankQ(int mem_cntrl, int cycles) {
913 m_mc_profilers[mem_cntrl]->m_memBankQ += cycles;
914}
915
916void Profiler::profileMemArbWait(int mem_cntrl, int cycles) {
917 m_mc_profilers[mem_cntrl]->m_memArbWait += cycles;
918}
919
920void Profiler::profileMemRandBusy(int mem_cntrl) {
921 m_mc_profilers[mem_cntrl]->m_memRandBusy++;
922}
923
924void Profiler::profileMemNotOld(int mem_cntrl) {
925 m_mc_profilers[mem_cntrl]->m_memNotOld++;
926}
927
928
929Profiler *
930RubyProfilerParams::create()
931{
932 return new Profiler(this);
933}
741Profiler *
742RubyProfilerParams::create()
743{
744 return new Profiler(this);
745}