1413//---- begin Transactional Memory CODE
1414void Profiler::profileTransaction(int size, int logSize, int readS, int writeS, int overflow_readS, int overflow_writeS, int retries, int useful_cycles, bool nacked, int loadMisses, int storeMisses, int instrCount, int xid){
1415 m_xactLogs.add(logSize);
1416 m_xactSizes.add(size);
1417 m_xactReads.add(readS);
1418 m_xactWrites.add(writeS);
1419 m_xactRetries.add(retries);
1420 m_xactCycles.add(useful_cycles);
1421 m_xactLoadMisses.add(loadMisses);
1422 m_xactStoreMisses.add(storeMisses);
1423 m_xactInstrCount.add(instrCount);
1424
1425 // was this transaction nacked?
1426 if(nacked){
1427 m_xactNacked++;
1428 }
1429
1430 // for overflowed transactions
1431 if(overflow_readS > 0 || overflow_writeS > 0){
1432 m_xactOverflowReads.add(overflow_readS);
1433 m_xactOverflowWrites.add(overflow_writeS);
1434 m_xactOverflowTotalReads.add(readS);
1435 m_xactOverflowTotalWrites.add(writeS);
1436 }
1437
1438 // Record commits by xid
1439 if(!m_commitIDMap_ptr->exist(xid)){
1440 m_commitIDMap_ptr->add(xid, 1);
1441 m_xactRetryIDMap_ptr->add(xid, retries);
1442 m_xactCyclesIDMap_ptr->add(xid, useful_cycles);
1443 m_xactReadSetIDMap_ptr->add(xid, readS);
1444 m_xactWriteSetIDMap_ptr->add(xid, writeS);
1445 m_xactLoadMissIDMap_ptr->add(xid, loadMisses);
1446 m_xactStoreMissIDMap_ptr->add(xid, storeMisses);
1447 m_xactInstrCountIDMap_ptr->add(xid, instrCount);
1448 } else {
1449 (m_commitIDMap_ptr->lookup(xid))++;
1450 (m_xactRetryIDMap_ptr->lookup(xid)) += retries;
1451 (m_xactCyclesIDMap_ptr->lookup(xid)) += useful_cycles;
1452 (m_xactReadSetIDMap_ptr->lookup(xid)) += readS;
1453 (m_xactWriteSetIDMap_ptr->lookup(xid)) += writeS;
1454 (m_xactLoadMissIDMap_ptr->lookup(xid)) += loadMisses;
1455 (m_xactStoreMissIDMap_ptr->lookup(xid)) += storeMisses;
1456 (m_xactInstrCountIDMap_ptr->lookup(xid)) += instrCount;
1457 }
1458}
1459
1460void Profiler::profileBeginTransaction(NodeID id, int tid, int xid, int thread, Address pc, bool isOpen){
1461 //- if(PROFILE_XACT){
1462 if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 2)){
1463 const char* openStr = isOpen ? " OPEN" : " CLOSED";
1464 const int ID_SPACES = 3;
1465 const int TIME_SPACES = 7;
1466 physical_address_t myPhysPC = SIMICS_translate_address(id, pc);
1467 integer_t myInst = SIMICS_read_physical_memory(id, myPhysPC, 4);
1468 const char *myInstStr = SIMICS_disassemble_physical(id, myPhysPC);
1469 // The actual processor number
1470 int proc_no = id*RubyConfig::numberofSMTThreads() + thread;
1471 (* debug_cout_ptr).flags(ios::right);
1472 (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
1473 (* debug_cout_ptr) << setw(ID_SPACES) << proc_no << " [" << id << "," << thread << "]" << " TID " << tid
1474 << " XACT BEGIN " << xid
1475 << " PC 0x" << hex << pc.getAddress()
1476 << dec
1477 << " *PC 0x" << hex << myInst << dec
1478 << " '" << myInstStr << "'"
1479 << openStr
1480 << endl;
1481 }
1482}
1483
1484void Profiler::profileCommitTransaction(NodeID id, int tid, int xid, int thread, Address pc, bool isOpen){
1485 //- if(PROFILE_XACT){
1486 if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 2)){
1487 const char* openStr = isOpen ? " OPEN" : " CLOSED";
1488 const int ID_SPACES = 3;
1489 const int TIME_SPACES = 7;
1490 physical_address_t myPhysPC = SIMICS_translate_address(id, pc);
1491 integer_t myInst = SIMICS_read_physical_memory(id, myPhysPC, 4);
1492 const char *myInstStr = SIMICS_disassemble_physical(id, myPhysPC);
1493 // The actual processor number
1494 int proc_no = id*RubyConfig::numberofSMTThreads() + thread;
1495 (* debug_cout_ptr).flags(ios::right);
1496 (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
1497 (* debug_cout_ptr) << setw(ID_SPACES) << proc_no << " [" << id << "," << thread << "]" << " TID " << tid
1498 << " XACT COMMIT " << xid
1499 << " PC 0x" << hex << pc.getAddress()
1500 << dec
1501 << " *PC 0x" << hex << myInst << dec
1502 << " '" << myInstStr << "'"
1503 << openStr
1504 << endl;
1505 }
1506
1507}
1508
1509// for profiling overflows
1510void Profiler::profileLoadOverflow(NodeID id, int tid, int xid, int thread, Address addr, bool l1_overflow){
1511 //- if(PROFILE_XACT){
1512 if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 1)){
1513 const int ID_SPACES = 3;
1514 const int TIME_SPACES = 7;
1515 string overflow_str = " XACT LOAD L1 OVERFLOW ";
1516 if(!l1_overflow){
1517 overflow_str = " XACT LOAD L2 OVERFLOW ";
1518 }
1519 // The actual processor number
1520 int proc_no = id*RubyConfig::numberofSMTThreads() + thread;
1521 (* debug_cout_ptr).flags(ios::right);
1522 (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
1523 (* debug_cout_ptr) << setw(ID_SPACES) << proc_no << " [" << id << "," << thread << "]" << " TID " << tid
1524 << overflow_str << xid
1525 << " ADDR " << addr
1526 << endl;
1527 }
1528}
1529
1530// for profiling overflows
1531void Profiler::profileStoreOverflow(NodeID id, int tid, int xid, int thread, Address addr, bool l1_overflow){
1532 //- if(PROFILE_XACT){
1533 if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 1)){
1534 const int ID_SPACES = 3;
1535 const int TIME_SPACES = 7;
1536 string overflow_str = " XACT STORE L1 OVERFLOW ";
1537 if(!l1_overflow){
1538 overflow_str = " XACT STORE L2 OVERFLOW ";
1539 }
1540 // The actual processor number
1541 int proc_no = id*RubyConfig::numberofSMTThreads() + thread;
1542 (* debug_cout_ptr).flags(ios::right);
1543 (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
1544 (* debug_cout_ptr) << setw(ID_SPACES) << proc_no << " [" << id << "," << thread << "]" << " TID " << tid
1545 << overflow_str << xid
1546 << " ADDR " << addr
1547 << endl;
1548 }
1549}
1550
1551void Profiler::profileLoadTransaction(NodeID id, int tid, int xid, int thread, Address addr, Address logicalAddress, Address pc){
1552 //- if(PROFILE_XACT){
1553 if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 3)){
1554 const int ID_SPACES = 3;
1555 const int TIME_SPACES = 7;
1556 physical_address_t myPhysPC = SIMICS_translate_address(id, pc);
1557 integer_t myInst = SIMICS_read_physical_memory(id, myPhysPC, 4);
1558 const char *myInstStr = SIMICS_disassemble_physical(id, myPhysPC);
1559 // The actual processor number
1560 int proc_no = id*RubyConfig::numberofSMTThreads() + thread;
1561 (* debug_cout_ptr).flags(ios::right);
1562 (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
1563 (* debug_cout_ptr) << setw(ID_SPACES) << proc_no << " [" << id << "," << thread << "]" << " TID " << tid
1564 << " XACT LOAD " << xid
1565 << " " << addr
1566 << " VA " << logicalAddress
1567 << " PC " << pc
1568 << " *PC 0x" << hex << myInst << dec
1569 << " '" << myInstStr << "'"
1570 //<< " VAL 0x" << hex << SIMICS_read_physical_memory(proc_no, SIMICS_translate_data_address(proc_no, logicalAddress), 4) << dec
1571 << " VAL 0x" << hex << g_system_ptr->getDriver()->readPhysicalMemory(proc_no, addr.getAddress(), 4) << dec
1572 << endl;
1573 }
1574}
1575
1576void Profiler::profileLoad(NodeID id, int tid, int xid, int thread, Address addr, Address logicalAddress, Address pc){
1577 if(PROFILE_NONXACT){
1578 const int ID_SPACES = 3;
1579 const int TIME_SPACES = 7;
1580 // The actual processor number
1581 int proc_no = id*RubyConfig::numberofSMTThreads() + thread;
1582 (* debug_cout_ptr).flags(ios::right);
1583 (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
1584 (* debug_cout_ptr) << setw(ID_SPACES) << proc_no << " [" << id << "," << thread << "]" << " TID " << tid
1585 << " LOAD " << xid
1586 << " " << addr
1587 << " VA " << logicalAddress
1588 << " PC " << pc
1589 //<< " VAL 0x" << hex << SIMICS_read_physical_memory(proc_no, SIMICS_translate_data_address(proc_no, logicalAddress), 4) << dec
1590 << " VAL 0x" << hex << g_system_ptr->getDriver()->readPhysicalMemory(proc_no, addr.getAddress(), 4) << dec
1591 << endl;
1592 }
1593}
1594
1595void Profiler::profileStoreTransaction(NodeID id, int tid, int xid, int thread, Address addr, Address logicalAddress, Address pc){
1596 //- if(PROFILE_XACT){
1597 if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 3)){
1598 const int ID_SPACES = 3;
1599 const int TIME_SPACES = 7;
1600 physical_address_t myPhysPC = SIMICS_translate_address(id, pc);
1601 integer_t myInst = SIMICS_read_physical_memory(id, myPhysPC, 4);
1602 const char *myInstStr = SIMICS_disassemble_physical(id, myPhysPC);
1603 // The actual processor number
1604 int proc_no = id*RubyConfig::numberofSMTThreads() + thread;
1605 (* debug_cout_ptr).flags(ios::right);
1606 (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
1607 (* debug_cout_ptr) << setw(ID_SPACES) << proc_no << " [" << id << "," << thread << "]" << " TID " << tid
1608 << " XACT STORE " << xid
1609 << " " << addr
1610 << " VA " << logicalAddress
1611 << " PC " << pc
1612 << " *PC 0x" << hex << myInst << dec
1613 << " '" << myInstStr << "'"
1614 << endl;
1615 }
1616}
1617
1618void Profiler::profileStore(NodeID id, int tid, int xid, int thread, Address addr, Address logicalAddress, Address pc){
1619 if(PROFILE_NONXACT){
1620 const int ID_SPACES = 3;
1621 const int TIME_SPACES = 7;
1622 // The actual processor number
1623 int proc_no = id*RubyConfig::numberofSMTThreads() + thread;
1624 (* debug_cout_ptr).flags(ios::right);
1625 (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
1626 (* debug_cout_ptr) << setw(ID_SPACES) << proc_no << " [" << id << "," << thread << "]" << " TID " << tid
1627 << " STORE " << xid
1628 << " " << addr
1629 << " VA " << logicalAddress
1630 << " PC " << pc
1631 << endl;
1632 }
1633}
1634
1635void Profiler::profileNack(NodeID id, int tid, int xid, int thread, int nacking_thread, NodeID nackedBy, Address addr, Address logicalAddress, Address pc, uint64 seq_ts, uint64 nack_ts, bool possibleCycle){
1636 int nid = 0; // g_system_ptr->getChip(nackedBy/RubyConfig::numberOfProcsPerChip())->getTransactionInterfaceManager(nackedBy%RubyConfig::numberOfProcsPerChip())->getXID(nacking_thread);
1637 assert(0);
1638 //- if(PROFILE_XACT){
1639 if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 1)){
1640 const int ID_SPACES = 3;
1641 const int TIME_SPACES = 7;
1642 physical_address_t myPhysPC = SIMICS_translate_address(id, pc);
1643 integer_t myInst = SIMICS_read_physical_memory(id, myPhysPC, 4);
1644 const char *myInstStr = SIMICS_disassemble_physical(id, myPhysPC);
1645 // The actual processor number
1646 int proc_no = id*g_NUM_SMT_THREADS + thread;
1647 int nack_proc_no = nackedBy*g_NUM_SMT_THREADS + nacking_thread;
1648 Address nack_pc = SIMICS_get_program_counter(nack_proc_no);
1649 (* debug_cout_ptr).flags(ios::right);
1650 (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
1651 (* debug_cout_ptr) << setw(ID_SPACES) << proc_no << " [" << id << "," << thread << "]" << " TID " << tid
1652 << " XACT NACK " << xid
1653 << " by " << nack_proc_no
1654 << " [ " << nackedBy
1655 << ", " << nacking_thread
1656 << " ]"
1657 << " NID: " << nid
1658 << " " << addr
1659 << " VA " << logicalAddress
1660 << " PC " << pc
1661 << " *PC 0x" << hex << myInst << dec
1662 << " '" << myInstStr << "'"
1663 << " NackerPC " << nack_pc
1664 << " my_ts " << seq_ts
1665 << " nack_ts " << nack_ts
1666 << " possible_cycle " << possibleCycle
1667 << endl;
1668 }
1669
1670 // Record nacks by xid
1671 if(!m_nackXIDMap_ptr->exist(xid)){
1672 m_nackXIDMap_ptr->add(xid, 1);
1673 } else {
1674 (m_nackXIDMap_ptr->lookup(xid))++;
1675 }
1676
1677 // Record nack ID pairs by xid
1678 if(!m_nackXIDPairMap_ptr->exist(xid)){
1679 Map<int, int> * new_map = new Map<int, int>;
1680 new_map->add(nid, 1);
1681 m_nackXIDPairMap_ptr->add(xid, new_map);
1682 }
1683 else{
1684 // retrieve existing map
1685 Map<int, int> * my_map = m_nackXIDPairMap_ptr->lookup(xid);
1686 if(!my_map->exist(nid)){
1687 my_map->add(nid, 1);
1688 }
1689 else{
1690 (my_map->lookup(nid))++;
1691 }
1692 }
1693
1694 // Record nacks by pc
1695 if(!m_nackPCMap_ptr->exist(pc)){
1696 m_nackPCMap_ptr->add(pc, 1);
1697 } else {
1698 (m_nackPCMap_ptr->lookup(pc))++;
1699 }
1700}
1701
1702void Profiler::profileExposedConflict(NodeID id, int xid, int thread, Address addr, Address pc){
1703 //if(PROFILE_XACT){
1704 const int ID_SPACES = 3;
1705 const int TIME_SPACES = 7;
1706 // The actual processor number
1707 int proc_no = id*g_NUM_SMT_THREADS + thread;
1708 (* debug_cout_ptr).flags(ios::right);
1709 (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
1710 (* debug_cout_ptr) << setw(ID_SPACES) << proc_no << " [" << id << "," << thread << "]" << " "
1711 << " EXPOSED ACTION CONFLICT " << xid
1712 << " ADDR " << addr
1713 << " PC " << pc
1714 << endl;
1715 //}
1716}
1717
1718void Profiler::profileInferredAbort(){
1719 m_inferredAborts++;
1720}
1721
1722void Profiler::profileAbortDelayConstants(int startupDelay, int perBlock){
1723 m_abortStarupDelay = startupDelay;
1724 m_abortPerBlockDelay = perBlock;
1725}
1726
1727void Profiler::profileAbortTransaction(NodeID id, int tid, int xid, int thread, int delay, int abortingThread, int abortingProc, Address addr, Address pc){
1728 const int ID_SPACES = 3;
1729 const int TIME_SPACES = 7;
1730 int abortingXID = -1;
1731 // The actual processor number
1732 int proc_no = id*g_NUM_SMT_THREADS + thread;
1733 // we are passed in physical proc number. Compute logical abort proc_no
1734 int logical_abort_proc_no = abortingProc/g_NUM_SMT_THREADS;
1735 if(abortingProc >= 0){
1736 AbstractChip * c = g_system_ptr->getChip(logical_abort_proc_no/RubyConfig::numberOfProcsPerChip());
1737 abortingXID = 0; // c->getTransactionInterfaceManager(logical_abort_proc_no%RubyConfig::numberOfProcsPerChip())->getXID(abortingThread);
1738 assert(0);
1739 }
1740 //- if(PROFILE_XACT){
1741 if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 1)){
1742 physical_address_t myPhysPC = SIMICS_translate_address(id, pc);
1743 integer_t myInst = SIMICS_read_physical_memory(id, myPhysPC, 4);
1744 const char *myInstStr = SIMICS_disassemble_physical(id, myPhysPC);
1745 (* debug_cout_ptr).flags(ios::right);
1746 (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
1747 (* debug_cout_ptr) << setw(ID_SPACES) << proc_no << " [" << id << "," << thread << "]" << " TID " << tid
1748 << " XACT ABORT " << xid
1749 << " caused by " << abortingProc
1750 << " [ " << logical_abort_proc_no
1751 << ", " << abortingThread
1752 << " ]"
1753 << " xid: " << abortingXID << " "
1754 << " address: " << addr
1755 << " delay: " << delay
1756 << " PC " << pc
1757 << " *PC 0x" << hex << myInst << dec
1758 << " '" << myInstStr << "'"
1759 << endl;
1760 }
1761 m_transactionAborts++;
1762
1763 // Record aborts by xid
1764 if(!m_abortIDMap_ptr->exist(xid)){
1765 m_abortIDMap_ptr->add(xid, 1);
1766 } else {
1767 (m_abortIDMap_ptr->lookup(xid))++;
1768 }
1769 m_abortDelays.add(delay);
1770
1771 // Record aborts by pc
1772 if(!m_abortPCMap_ptr->exist(pc)){
1773 m_abortPCMap_ptr->add(pc, 1);
1774 } else {
1775 (m_abortPCMap_ptr->lookup(pc))++;
1776 }
1777
1778 // Record aborts by address
1779 if(!m_abortAddressMap_ptr->exist(addr)){
1780 m_abortAddressMap_ptr->add(addr, 1);
1781 } else {
1782 (m_abortAddressMap_ptr->lookup(addr))++;
1783 }
1784}
1785
1786void Profiler::profileTransWB(){
1787 m_transWBs++;
1788}
1789
1790void Profiler::profileExtraWB(){
1791 m_extraWBs++;
1792}
1793
1794void Profiler::profileXactChange(int procs, int cycles){
1795 if(!m_procsInXactMap_ptr->exist(procs)){
1796 m_procsInXactMap_ptr->add(procs, cycles);
1797 } else {
1798 (m_procsInXactMap_ptr->lookup(procs)) += cycles;
1799 }
1800}
1801
1802void Profiler::profileReadSet(Address addr, bool bf_filter_result, bool perfect_filter_result, NodeID id, int thread){
1803 // do NOT count instances when signature is empty!
1804 if(!bf_filter_result && !perfect_filter_result){
1805 m_readSetEmptyChecks++;
1806 return;
1807 }
1808
1809 if(bf_filter_result != perfect_filter_result){
1810 m_readSetNoMatch++;
1811 /*
1812 // we have a false positive
1813 if(!m_readSetNoMatch_ptr->exist(addr)){
1814 m_readSetNoMatch_ptr->add(addr, 1);
1815 }
1816 else{
1817 (m_readSetNoMatch_ptr->lookup(addr))++;
1818 }
1819 */
1820 }
1821 else{
1822 m_readSetMatch++;
1823 /*
1824 // Bloom filter agrees with perfect filter
1825 if(!m_readSetMatch_ptr->exist(addr)){
1826 m_readSetMatch_ptr->add(addr, 1);
1827 }
1828 else{
1829 (m_readSetMatch_ptr->lookup(addr))++;
1830 }
1831 */
1832 }
1833}
1834
1835
1836void Profiler::profileRemoteReadSet(Address addr, bool bf_filter_result, bool perfect_filter_result, NodeID id, int thread){
1837 if(bf_filter_result != perfect_filter_result){
1838 // we have a false positive
1839 if(!m_remoteReadSetNoMatch_ptr->exist(addr)){
1840 m_remoteReadSetNoMatch_ptr->add(addr, 1);
1841 }
1842 else{
1843 (m_remoteReadSetNoMatch_ptr->lookup(addr))++;
1844 }
1845 }
1846 else{
1847 // Bloom filter agrees with perfect filter
1848 if(!m_remoteReadSetMatch_ptr->exist(addr)){
1849 m_remoteReadSetMatch_ptr->add(addr, 1);
1850 }
1851 else{
1852 (m_remoteReadSetMatch_ptr->lookup(addr))++;
1853 }
1854 }
1855}
1856
1857void Profiler::profileWriteSet(Address addr, bool bf_filter_result, bool perfect_filter_result, NodeID id, int thread){
1858 // do NOT count instances when signature is empty!
1859 if(!bf_filter_result && !perfect_filter_result){
1860 m_writeSetEmptyChecks++;
1861 return;
1862 }
1863
1864 if(bf_filter_result != perfect_filter_result){
1865 m_writeSetNoMatch++;
1866 /*
1867 // we have a false positive
1868 if(!m_writeSetNoMatch_ptr->exist(addr)){
1869 m_writeSetNoMatch_ptr->add(addr, 1);
1870 }
1871 else{
1872 (m_writeSetNoMatch_ptr->lookup(addr))++;
1873 }
1874 */
1875 }
1876 else{
1877 m_writeSetMatch++;
1878 /*
1879 // Bloom filter agrees with perfect filter
1880 if(!m_writeSetMatch_ptr->exist(addr)){
1881 m_writeSetMatch_ptr->add(addr, 1);
1882 }
1883 else{
1884 (m_writeSetMatch_ptr->lookup(addr))++;
1885 }
1886 */
1887 }
1888}
1889
1890
1891void Profiler::profileRemoteWriteSet(Address addr, bool bf_filter_result, bool perfect_filter_result, NodeID id, int thread){
1892 if(bf_filter_result != perfect_filter_result){
1893 // we have a false positive
1894 if(!m_remoteWriteSetNoMatch_ptr->exist(addr)){
1895 m_remoteWriteSetNoMatch_ptr->add(addr, 1);
1896 }
1897 else{
1898 (m_remoteWriteSetNoMatch_ptr->lookup(addr))++;
1899 }
1900 }
1901 else{
1902 // Bloom filter agrees with perfect filter
1903 if(!m_remoteWriteSetMatch_ptr->exist(addr)){
1904 m_remoteWriteSetMatch_ptr->add(addr, 1);
1905 }
1906 else{
1907 (m_remoteWriteSetMatch_ptr->lookup(addr))++;
1908 }
1909 }
1910}
1911
1912void Profiler::profileTransactionLogOverflow(NodeID id, Address addr, Address pc){
1913 if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 1)){
1914 const int ID_SPACES = 3;
1915 const int TIME_SPACES = 7;
1916 physical_address_t myPhysPC = SIMICS_translate_address(id, pc);
1917 integer_t myInst = SIMICS_read_physical_memory(id, myPhysPC, 4);
1918 const char *myInstStr = SIMICS_disassemble_physical(id, myPhysPC);
1919 (* debug_cout_ptr).flags(ios::right);
1920 (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
1921 (* debug_cout_ptr) << setw(ID_SPACES) << id << " "
1922 << " XACT LOG OVERFLOW"
1923 << " ADDR " << addr
1924 << " PC " << pc
1925 << " *PC 0x" << hex << myInst << dec
1926 << " '" << myInstStr << "'"
1927 << endl;
1928
1929 }
1930 m_transactionLogOverflows++;
1931}
1932
1933void Profiler::profileTransactionCacheOverflow(NodeID id, Address addr, Address pc){
1934 if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 1)){
1935 const int ID_SPACES = 3;
1936 const int TIME_SPACES = 7;
1937 physical_address_t myPhysPC = SIMICS_translate_address(id, pc);
1938 integer_t myInst = SIMICS_read_physical_memory(id, myPhysPC, 4);
1939 const char *myInstStr = SIMICS_disassemble_physical(id, myPhysPC);
1940 (* debug_cout_ptr).flags(ios::right);
1941 (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
1942 (* debug_cout_ptr) << setw(ID_SPACES) << id << " "
1943 << " XACT CACHE OVERFLOW "
1944 << " ADDR " << addr
1945 << " PC " << pc
1946 << " *PC 0x" << hex << myInst << dec
1947 << " '" << myInstStr << "'"
1948 << endl;
1949
1950 }
1951 m_transactionCacheOverflows++;
1952}
1953
1954void Profiler::profileGetCPS(NodeID id, uint32 cps, Address pc){
1955 if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 1)){
1956 const int ID_SPACES = 3;
1957 const int TIME_SPACES = 7;
1958 physical_address_t myPhysPC = SIMICS_translate_address(id, pc);
1959 integer_t myInst = SIMICS_read_physical_memory(id, myPhysPC, 4);
1960 const char *myInstStr = SIMICS_disassemble_physical(id, myPhysPC);
1961
1962 (* debug_cout_ptr).flags(ios::right);
1963 (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
1964 (* debug_cout_ptr) << setw(ID_SPACES) << id << " "
1965 << " XACT GET CPS"
1966 << " PC " << pc
1967 << " *PC 0x" << hex << myInst << dec
1968 << " '" << myInstStr << "'"
1969 << " CPS 0x" << hex << cps << dec
1970 << endl;
1971 }
1972}
1973//---- end Transactional Memory CODE
1974
1975
1976void Profiler::profileExceptionStart(bool xact, NodeID id, int thread, int val, int trap_level, uinteger_t pc, uinteger_t npc){
1977 if(xact){
1978 if(!m_xactExceptionMap_ptr->exist(val)){
1979 m_xactExceptionMap_ptr->add(val, 1);
1980 } else {
1981 (m_xactExceptionMap_ptr->lookup(val))++;
1982 }
1983 }
1984
1985 if (!xact && !PROFILE_NONXACT) return;
1986
1987 if(PROFILE_EXCEPTIONS){
1988 const int ID_SPACES = 3;
1989 const int TIME_SPACES = 7;
1990 // The actual processor number
1991 int proc_no = id*g_NUM_SMT_THREADS + thread;
1992
1993 // get the excepting instruction
1994 const char * instruction;
1995 physical_address_t addr = SIMICS_translate_address( proc_no, Address(pc));
1996 if(val != 0x64 && addr != 0x0){
1997 // ignore instruction TLB miss
1998 instruction = SIMICS_disassemble_physical( proc_no, addr );
1999 }
2000
2001 (* debug_cout_ptr).flags(ios::right);
2002 (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
2003 (* debug_cout_ptr) << setw(ID_SPACES) << proc_no << " [" << id << "," << thread << " ]" << " ";
2004 if (xact)
2005 (* debug_cout_ptr) << " XACT Exception(";
2006 else
2007 (* debug_cout_ptr) << " Exception(";
2008
2009 (* debug_cout_ptr) << hex << val << dec << ")_START--Trap Level " << trap_level
2010 << "--(PC=0x" << hex << pc << ", " << npc << ")"
2011 << dec;
2012
2013 if(val != 0x64 && addr != 0x0){
2014 (* debug_cout_ptr) << " instruction = " << instruction;
2015 }
2016 else{
2017 (* debug_cout_ptr) << " instruction = INSTRUCTION TLB MISS";
2018 }
2019 (* debug_cout_ptr) << dec << endl;
2020 }
2021}
2022
2023void Profiler::profileExceptionDone(bool xact, NodeID id, int thread, int val, int trap_level, uinteger_t pc, uinteger_t npc, uinteger_t tpc, uinteger_t tnpc){
2024 if (!xact && !PROFILE_NONXACT) return;
2025
2026 if (PROFILE_EXCEPTIONS){
2027 const int ID_SPACES = 3;
2028 const int TIME_SPACES = 7;
2029 // The actual processor number
2030 int proc_no = id*g_NUM_SMT_THREADS + thread;
2031
2032 // get the excepting instruction
2033 const char * instruction;
2034 instruction = SIMICS_disassemble_physical( proc_no, SIMICS_translate_address( proc_no, Address(pc) ) );
2035
2036
2037 (* debug_cout_ptr).flags(ios::right);
2038 (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
2039 (* debug_cout_ptr) << setw(ID_SPACES) << proc_no << " [" << id << "," << thread << " ]" << " ";
2040 if (xact)
2041 (* debug_cout_ptr) << " XACT Exception(";
2042 else
2043 (* debug_cout_ptr) << " Exception(";
2044
2045 (* debug_cout_ptr) << hex << val << dec << ")_DONE--Trap Level " << trap_level
2046 << "--(PC=0x" << hex << pc << ", " << npc << dec << ")"
2047 << "--(TPC=0x" << hex << tpc << ", " << tnpc << dec << ")"
2048 << endl;
2049 }
2050}
2051
2052void Profiler::rubyWatch(int id){
2053 int rn_g1 = SIMICS_get_register_number(id, "g1");
2054 uint64 tr = SIMICS_read_register(id, rn_g1);
2055 Address watch_address = Address(tr);
2056 const int ID_SPACES = 3;
2057 const int TIME_SPACES = 7;
2058
2059 (* debug_cout_ptr).flags(ios::right);
2060 (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
2061 (* debug_cout_ptr) << setw(ID_SPACES) << id << " "
2062 << "RUBY WATCH "
2063 << watch_address
2064 << endl;
2065
2066 if(!m_watch_address_list_ptr->exist(watch_address)){
2067 m_watch_address_list_ptr->add(watch_address, 1);
2068 }
2069}
2070
2071bool Profiler::watchAddress(Address addr){
2072 if (m_watch_address_list_ptr->exist(addr))
2073 return true;
2074 else
2075 return false;
2076}
2077
2078void Profiler::profileReadFilterBitsSet(int xid, int bits, bool isCommit) {
2079 if (isCommit) {
2080 if(!m_xactReadFilterBitsSetOnCommit->exist(xid)){
2081 Histogram hist;
2082 hist.add(bits);
2083 m_xactReadFilterBitsSetOnCommit->add(xid, hist);
2084 }
2085 else{
2086 (m_xactReadFilterBitsSetOnCommit->lookup(xid)).add(bits);
2087 }
2088 } else {
2089 if(!m_xactReadFilterBitsSetOnAbort->exist(xid)){
2090 Histogram hist;
2091 hist.add(bits);
2092 m_xactReadFilterBitsSetOnAbort->add(xid, hist);
2093 }
2094 else{
2095 (m_xactReadFilterBitsSetOnAbort->lookup(xid)).add(bits);
2096 }
2097 }
2098}
2099
2100void Profiler::profileWriteFilterBitsSet(int xid, int bits, bool isCommit) {
2101 if (isCommit) {
2102 if(!m_xactWriteFilterBitsSetOnCommit->exist(xid)){
2103 Histogram hist;
2104 hist.add(bits);
2105 m_xactWriteFilterBitsSetOnCommit->add(xid, hist);
2106 }
2107 else{
2108 (m_xactWriteFilterBitsSetOnCommit->lookup(xid)).add(bits);
2109 }
2110 } else {
2111 if(!m_xactWriteFilterBitsSetOnAbort->exist(xid)){
2112 Histogram hist;
2113 hist.add(bits);
2114 m_xactWriteFilterBitsSetOnAbort->add(xid, hist);
2115 }
2116 else{
2117 (m_xactWriteFilterBitsSetOnAbort->lookup(xid)).add(bits);
2118 }
2119 }
2120}
2121/*
2122 //gem5:Arka for decomissioning log_tm
2123
2124void Profiler::setXactVisualizerFile(char * filename){
2125 if ( (filename == NULL) ||
2126 (!strcmp(filename, "none")) ) {
2127 m_xact_visualizer_ptr = &cout;
2128 return;
2129 }
2130
2131 if (m_xact_visualizer.is_open() ) {
2132 m_xact_visualizer.close ();
2133 }
2134 m_xact_visualizer.open (filename, std::ios::out);
2135 if (! m_xact_visualizer.is_open() ) {
2136 cerr << "setXactVisualizer: can't open file " << filename << endl;
2137 }
2138 else {
2139 m_xact_visualizer_ptr = &m_xact_visualizer;
2140 }
2141 cout << "setXactVisualizer file " << filename << endl;
2142}
2143
2144void Profiler::printTransactionState(bool can_skip){
2145 if (!XACT_VISUALIZER) return;
2146 int num_processors = RubyConfig::numberOfProcessors() * RubyConfig::numberofSMTThreads();
2147
2148 if (!g_system_ptr->getXactVisualizer()->existXactActivity() && can_skip)
2149 return;
2150
2151 if (can_skip && ((g_eventQueue_ptr->getTime()/10000) <= m_xact_visualizer_last))
2152 return;
2153
2154 Vector<char> xactStateVector = g_system_ptr->getXactVisualizer()->getTransactionStateVector();
2155 for (int i = 0 ; i < num_processors; i++){
2156 (* m_xact_visualizer_ptr) << xactStateVector[i] << " ";
2157 }
2158 (* m_xact_visualizer_ptr) << " " << g_eventQueue_ptr->getTime() << endl;
2159 m_xact_visualizer_last = g_eventQueue_ptr->getTime() / 10000;
2160}
2161*/
2162void Profiler::watchpointsFalsePositiveTrigger()
2163{
2164 m_watchpointsFalsePositiveTrigger++;
2165}
2166
2167void Profiler::watchpointsTrueTrigger()
2168{
2169 m_watchpointsTrueTrigger++;
2170}
2171
2172// For MemoryControl:
2173void Profiler::profileMemReq(int bank) {
2174 m_memReq++;
2175 m_memBankCount[bank]++;
2176}
2177void Profiler::profileMemBankBusy() { m_memBankBusy++; }
2178void Profiler::profileMemBusBusy() { m_memBusBusy++; }
2179void Profiler::profileMemReadWriteBusy() { m_memReadWriteBusy++; }
2180void Profiler::profileMemDataBusBusy() { m_memDataBusBusy++; }
2181void Profiler::profileMemTfawBusy() { m_memTfawBusy++; }
2182void Profiler::profileMemRefresh() { m_memRefresh++; }
2183void Profiler::profileMemRead() { m_memRead++; }
2184void Profiler::profileMemWrite() { m_memWrite++; }
2185void Profiler::profileMemWaitCycles(int cycles) { m_memWaitCycles += cycles; }
2186void Profiler::profileMemInputQ(int cycles) { m_memInputQ += cycles; }
2187void Profiler::profileMemBankQ(int cycles) { m_memBankQ += cycles; }
2188void Profiler::profileMemArbWait(int cycles) { m_memArbWait += cycles; }
2189void Profiler::profileMemRandBusy() { m_memRandBusy++; }
2190void Profiler::profileMemNotOld() { m_memNotOld++; }
2191
2192
2193//----------- ATMTP -------------------//
2194
2195void Profiler::profileTransactionTCC(NodeID id, Address pc){
2196 if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 1)){
2197 physical_address_t myPhysPC = SIMICS_translate_address(id, pc);
2198 integer_t myInst = SIMICS_read_physical_memory(id, myPhysPC, 4);
2199 const char *myInstStr = SIMICS_disassemble_physical(id, myPhysPC);
2200
2201 const int ID_SPACES = 3;
2202 const int TIME_SPACES = 7;
2203 cout.flags(ios::right);
2204 cout << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
2205 cout << setw(ID_SPACES) << id << " "
2206 << " XACT Aborting! Executed TCC "
2207 << " PC: " << pc
2208 << " *PC: 0x" << hex << myInst << dec
2209 << " '" << myInstStr << "'"
2210 << endl;
2211 }
2212 m_transactionUnsupInsts++;
2213}
2214
2215void Profiler::profileTransactionUnsupInst(NodeID id, Address pc){
2216 if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 1)){
2217 physical_address_t myPhysPC = SIMICS_translate_address(id, pc);
2218 integer_t myInst = SIMICS_read_physical_memory(id, myPhysPC, 4);
2219 const char *myInstStr = SIMICS_disassemble_physical(id, myPhysPC);
2220
2221 const int ID_SPACES = 3;
2222 const int TIME_SPACES = 7;
2223 cout.flags(ios::right);
2224 cout << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
2225 cout << setw(ID_SPACES) << id << " "
2226 << " XACT Aborting! Executed Unsupported Instruction "
2227 << " PC: " << pc
2228 << " *PC: 0x" << hex << myInst << dec
2229 << " '" << myInstStr << "'"
2230 << endl;
2231 }
2232 m_transactionUnsupInsts++;
2233}
2234
2235void Profiler::profileTransactionSaveInst(NodeID id, Address pc){
2236 if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 1)){
2237 physical_address_t myPhysPC = SIMICS_translate_address(id, pc);
2238 integer_t myInst = SIMICS_read_physical_memory(id, myPhysPC, 4);
2239 const char *myInstStr = SIMICS_disassemble_physical(id, myPhysPC);
2240
2241 const int ID_SPACES = 3;
2242 const int TIME_SPACES = 7;
2243 cout.flags(ios::right);
2244 cout << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
2245 cout << setw(ID_SPACES) << id << " "
2246 << " XACT Aborting! Executed Save Instruction "
2247 << " PC: " << pc
2248 << " *PC: 0x" << hex << myInst << dec
2249 << " '" << myInstStr << "'"
2250 << endl;
2251 }
2252 m_transactionSaveRestAborts++;
2253}
2254
2255void Profiler::profileTransactionRestoreInst(NodeID id, Address pc){
2256 if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 1)){
2257 physical_address_t myPhysPC = SIMICS_translate_address(id, pc);
2258 integer_t myInst = SIMICS_read_physical_memory(id, myPhysPC, 4);
2259 const char *myInstStr = SIMICS_disassemble_physical(id, myPhysPC);
2260
2261 const int ID_SPACES = 3;
2262 const int TIME_SPACES = 7;
2263 cout.flags(ios::right);
2264 cout << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
2265 cout << setw(ID_SPACES) << id << " "
2266 << " XACT Aborting! Executed Restore Instruction "
2267 << " PC: " << pc
2268 << " *PC: 0x" << hex << myInst << dec
2269 << " '" << myInstStr << "'"
2270 << endl;
2271 }
2272 m_transactionSaveRestAborts++;
2273}
2274
2275void Profiler::profileTimerInterrupt(NodeID id,
2276 uinteger_t tick, uinteger_t tick_cmpr,
2277 uinteger_t stick, uinteger_t stick_cmpr,
2278 int trap_level,
2279 uinteger_t pc, uinteger_t npc,
2280 uinteger_t pstate, int pil){
2281 if (PROFILE_EXCEPTIONS) {
2282 const int ID_SPACES = 3;
2283 const int TIME_SPACES = 7;
2284 cout.flags(ios::right);
2285 cout << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
2286 cout << setw(ID_SPACES) << id << " ";
2287 cout << hex << "Timer--(Tick=0x" << tick << ", TckCmp=0x" << tick_cmpr
2288 << ", STick=0x" << stick << ", STickCmp=0x" << stick_cmpr
2289 << ")--(PC=" << pc << ", " << npc
2290 << dec << ")--(TL=" << trap_level << ", pil=" << pil
2291 << hex << ", pstate=0x" << pstate
2292 << dec << ")" << endl;
2293 }
2294}
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