61d60
< #include "mem/ruby/common/Driver.hh"
76c75
< Profiler::Profiler()
---
> Profiler::Profiler(const string & name)
78a78
> m_name = name;
84a85,88
> m_inst_profiler_ptr = NULL;
> m_address_profiler_ptr = NULL;
>
> /*
87c91
< if (PROFILE_ALL_INSTRUCTIONS) {
---
> if (m_all_instructions) {
90c94
<
---
> */
96a101,102
> //changed by SS
> /*
119,120c125
<
< clearStats();
---
> */
135a141,205
> void Profiler::init(const vector<string> & argv, vector<string> memory_control_names)
> {
> // added by SS
> vector<string>::iterator it;
> memory_control_profiler* mcp;
> m_memory_control_names = memory_control_names;
> // printf ( "Here in Profiler::init \n");
> for ( it=memory_control_names.begin() ; it < memory_control_names.end(); it++ ){
> // printf ( "Here in Profiler::init memory control name %s \n", (*it).c_str());
> mcp = new memory_control_profiler;
> mcp->m_memReq = 0;
> mcp->m_memBankBusy = 0;
> mcp->m_memBusBusy = 0;
> mcp->m_memReadWriteBusy = 0;
> mcp->m_memDataBusBusy = 0;
> mcp->m_memTfawBusy = 0;
> mcp->m_memRefresh = 0;
> mcp->m_memRead = 0;
> mcp->m_memWrite = 0;
> mcp->m_memWaitCycles = 0;
> mcp->m_memInputQ = 0;
> mcp->m_memBankQ = 0;
> mcp->m_memArbWait = 0;
> mcp->m_memRandBusy = 0;
> mcp->m_memNotOld = 0;
>
> mcp->m_banks_per_rank = RubySystem::getMemoryControl((*it).c_str())->getBanksPerRank();
> mcp->m_ranks_per_dimm = RubySystem::getMemoryControl((*it).c_str())->getRanksPerDimm();
> mcp->m_dimms_per_channel = RubySystem::getMemoryControl((*it).c_str())->getDimmsPerChannel();
>
> int totalBanks = mcp->m_banks_per_rank
> * mcp->m_ranks_per_dimm
> * mcp->m_dimms_per_channel;
>
> mcp->m_memBankCount.setSize(totalBanks);
>
> m_memory_control_profilers [(*it).c_str()] = mcp;
> }
>
> clearStats();
> m_hot_lines = false;
> m_all_instructions = false;
>
> for (size_t i=0; i<argv.size(); i+=2) {
> if ( argv[i] == "hot_lines") {
> m_hot_lines = (argv[i+1]=="true");
> } else if ( argv[i] == "all_instructions") {
> m_all_instructions = (argv[i+1]=="true");
> }else {
> cerr << "WARNING: Profiler: Unkown configuration parameter: " << argv[i] << endl;
> assert(false);
> }
> }
>
> m_address_profiler_ptr = new AddressProfiler;
> m_address_profiler_ptr -> setHotLines(m_hot_lines);
> m_address_profiler_ptr -> setAllInstructions(m_all_instructions);
>
> if (m_all_instructions) {
> m_inst_profiler_ptr = new AddressProfiler;
> m_inst_profiler_ptr -> setHotLines(m_hot_lines);
> m_inst_profiler_ptr -> setAllInstructions(m_all_instructions);
> }
> }
>
141c211
< perProcInstructionCount.setSize(RubyConfig::numberOfProcessors());
---
> perProcInstructionCount.setSize(RubySystem::getNumberOfSequencers());
144c214
< perProcCycleCount.setSize(RubyConfig::numberOfProcessors());
---
> perProcCycleCount.setSize(RubySystem::getNumberOfSequencers());
146,148c216,218
< for(int i=0; i < RubyConfig::numberOfProcessors(); i++) {
< perProcInstructionCount[i] = g_system_ptr->getDriver()->getInstructionCount(i) - m_instructions_executed_at_start[i] + 1;
< perProcCycleCount[i] = g_system_ptr->getDriver()->getCycleCount(i) - m_cycles_executed_at_start[i] + 1;
---
> for(int i=0; i < RubySystem::getNumberOfSequencers(); i++) {
> perProcInstructionCount[i] = g_system_ptr->getInstructionCount(i) - m_instructions_executed_at_start[i] + 1;
> perProcCycleCount[i] = g_system_ptr->getCycleCount(i) - m_cycles_executed_at_start[i] + 1;
154c224
< integer_t cycles_executed = perProcCycleCount.sum();
---
> integer_t simics_cycles_executed = perProcCycleCount.sum();
161c231
< (*m_periodic_output_file_ptr) << "cycles_executed: " << cycles_executed << " " << perProcCycleCount << endl;
---
> (*m_periodic_output_file_ptr) << "simics_cycles_executed: " << simics_cycles_executed << " " << perProcCycleCount << endl;
175c245
< if (PROFILE_ALL_INSTRUCTIONS) {
---
> if (m_all_instructions) {
280,283c350,353
< perProcInstructionCount.setSize(RubyConfig::numberOfProcessors());
< perProcCycleCount.setSize(RubyConfig::numberOfProcessors());
< perProcCPI.setSize(RubyConfig::numberOfProcessors());
< perProcMissesPerInsn.setSize(RubyConfig::numberOfProcessors());
---
> perProcInstructionCount.setSize(RubySystem::getNumberOfSequencers());
> perProcCycleCount.setSize(RubySystem::getNumberOfSequencers());
> perProcCPI.setSize(RubySystem::getNumberOfSequencers());
> perProcMissesPerInsn.setSize(RubySystem::getNumberOfSequencers());
285,287c355,357
< perProcInsnPerTrans.setSize(RubyConfig::numberOfProcessors());
< perProcCyclesPerTrans.setSize(RubyConfig::numberOfProcessors());
< perProcMissesPerTrans.setSize(RubyConfig::numberOfProcessors());
---
> perProcInsnPerTrans.setSize(RubySystem::getNumberOfSequencers());
> perProcCyclesPerTrans.setSize(RubySystem::getNumberOfSequencers());
> perProcMissesPerTrans.setSize(RubySystem::getNumberOfSequencers());
289,291c359,361
< for(int i=0; i < RubyConfig::numberOfProcessors(); i++) {
< perProcInstructionCount[i] = g_system_ptr->getDriver()->getInstructionCount(i) - m_instructions_executed_at_start[i] + 1;
< perProcCycleCount[i] = g_system_ptr->getDriver()->getCycleCount(i) - m_cycles_executed_at_start[i] + 1;
---
> for(int i=0; i < RubySystem::getNumberOfSequencers(); i++) {
> perProcInstructionCount[i] = g_system_ptr->getInstructionCount(i) - m_instructions_executed_at_start[i] + 1;
> perProcCycleCount[i] = g_system_ptr->getCycleCount(i) - m_cycles_executed_at_start[i] + 1;
312c382
< integer_t cycles_executed = perProcCycleCount.sum();
---
> integer_t simics_cycles_executed = perProcCycleCount.sum();
317c387
< double cycles_per_transaction = (transactions_ended != 0) ? (RubyConfig::numberOfProcessors() * double(ruby_cycles)) / double(transactions_ended) : 0;
---
> double cycles_per_transaction = (transactions_ended != 0) ? (RubySystem::getNumberOfSequencers() * double(ruby_cycles)) / double(transactions_ended) : 0;
326,327c396,397
< out << "cycles_executed: " << cycles_executed << " " << perProcCycleCount << endl;
< out << "cycles_per_instruction: " << (RubyConfig::numberOfProcessors()*double(ruby_cycles))/double(instruction_executed) << " " << perProcCPI << endl;
---
> out << "ruby_cycles_executed: " << simics_cycles_executed << " " << perProcCycleCount << endl;
> out << "cycles_per_instruction: " << (RubySystem::getNumberOfSequencers()*double(ruby_cycles))/double(instruction_executed) << " " << perProcCPI << endl;
344,376c414,469
< if (m_memReq || m_memRefresh) { // if there's a memory controller at all
< long long int total_stalls = m_memInputQ + m_memBankQ + m_memWaitCycles;
< double stallsPerReq = total_stalls * 1.0 / m_memReq;
< out << "Memory control:" << endl;
< out << " memory_total_requests: " << m_memReq << endl; // does not include refreshes
< out << " memory_reads: " << m_memRead << endl;
< out << " memory_writes: " << m_memWrite << endl;
< out << " memory_refreshes: " << m_memRefresh << endl;
< out << " memory_total_request_delays: " << total_stalls << endl;
< out << " memory_delays_per_request: " << stallsPerReq << endl;
< out << " memory_delays_in_input_queue: " << m_memInputQ << endl;
< out << " memory_delays_behind_head_of_bank_queue: " << m_memBankQ << endl;
< out << " memory_delays_stalled_at_head_of_bank_queue: " << m_memWaitCycles << endl;
< // Note: The following "memory stalls" entries are a breakdown of the
< // cycles which already showed up in m_memWaitCycles. The order is
< // significant; it is the priority of attributing the cycles.
< // For example, bank_busy is before arbitration because if the bank was
< // busy, we didn't even check arbitration.
< // Note: "not old enough" means that since we grouped waiting heads-of-queues
< // into batches to avoid starvation, a request in a newer batch
< // didn't try to arbitrate yet because there are older requests waiting.
< out << " memory_stalls_for_bank_busy: " << m_memBankBusy << endl;
< out << " memory_stalls_for_random_busy: " << m_memRandBusy << endl;
< out << " memory_stalls_for_anti_starvation: " << m_memNotOld << endl;
< out << " memory_stalls_for_arbitration: " << m_memArbWait << endl;
< out << " memory_stalls_for_bus: " << m_memBusBusy << endl;
< out << " memory_stalls_for_tfaw: " << m_memTfawBusy << endl;
< out << " memory_stalls_for_read_write_turnaround: " << m_memReadWriteBusy << endl;
< out << " memory_stalls_for_read_read_turnaround: " << m_memDataBusBusy << endl;
< out << " accesses_per_bank: ";
< for (int bank=0; bank < m_memBankCount.size(); bank++) {
< out << m_memBankCount[bank] << " ";
< //if ((bank % 8) == 7) out << " " << endl;
---
> vector<string>::iterator it;
>
> for ( it=m_memory_control_names.begin() ; it < m_memory_control_names.end(); it++ ){
> long long int m_memReq = m_memory_control_profilers[(*it).c_str()] -> m_memReq;
> long long int m_memRefresh = m_memory_control_profilers[(*it).c_str()] -> m_memRefresh;
> long long int m_memInputQ = m_memory_control_profilers[(*it).c_str()] -> m_memInputQ;
> long long int m_memBankQ = m_memory_control_profilers[(*it).c_str()] -> m_memBankQ;
> long long int m_memWaitCycles = m_memory_control_profilers[(*it).c_str()] -> m_memWaitCycles;
> long long int m_memRead = m_memory_control_profilers[(*it).c_str()] -> m_memRead;
> long long int m_memWrite = m_memory_control_profilers[(*it).c_str()] -> m_memWrite;
> long long int m_memBankBusy = m_memory_control_profilers[(*it).c_str()] -> m_memBankBusy;
> long long int m_memRandBusy = m_memory_control_profilers[(*it).c_str()] -> m_memRandBusy;
> long long int m_memNotOld = m_memory_control_profilers[(*it).c_str()] -> m_memNotOld;
> long long int m_memArbWait = m_memory_control_profilers[(*it).c_str()] -> m_memArbWait;
> long long int m_memBusBusy = m_memory_control_profilers[(*it).c_str()] -> m_memBusBusy;
> long long int m_memTfawBusy = m_memory_control_profilers[(*it).c_str()] -> m_memTfawBusy;
> long long int m_memReadWriteBusy = m_memory_control_profilers[(*it).c_str()] -> m_memReadWriteBusy;
> long long int m_memDataBusBusy = m_memory_control_profilers[(*it).c_str()] -> m_memDataBusBusy;
> Vector<long long int> m_memBankCount = m_memory_control_profilers[(*it).c_str()] -> m_memBankCount;
>
> if (m_memReq || m_memRefresh) { // if there's a memory controller at all
> long long int total_stalls = m_memInputQ + m_memBankQ + m_memWaitCycles;
> double stallsPerReq = total_stalls * 1.0 / m_memReq;
> out << "Memory control:" << endl;
> out << " memory_total_requests: " << m_memReq << endl; // does not include refreshes
> out << " memory_reads: " << m_memRead << endl;
> out << " memory_writes: " << m_memWrite << endl;
> out << " memory_refreshes: " << m_memRefresh << endl;
> out << " memory_total_request_delays: " << total_stalls << endl;
> out << " memory_delays_per_request: " << stallsPerReq << endl;
> out << " memory_delays_in_input_queue: " << m_memInputQ << endl;
> out << " memory_delays_behind_head_of_bank_queue: " << m_memBankQ << endl;
> out << " memory_delays_stalled_at_head_of_bank_queue: " << m_memWaitCycles << endl;
> // Note: The following "memory stalls" entries are a breakdown of the
> // cycles which already showed up in m_memWaitCycles. The order is
> // significant; it is the priority of attributing the cycles.
> // For example, bank_busy is before arbitration because if the bank was
> // busy, we didn't even check arbitration.
> // Note: "not old enough" means that since we grouped waiting heads-of-queues
> // into batches to avoid starvation, a request in a newer batch
> // didn't try to arbitrate yet because there are older requests waiting.
> out << " memory_stalls_for_bank_busy: " << m_memBankBusy << endl;
> out << " memory_stalls_for_random_busy: " << m_memRandBusy << endl;
> out << " memory_stalls_for_anti_starvation: " << m_memNotOld << endl;
> out << " memory_stalls_for_arbitration: " << m_memArbWait << endl;
> out << " memory_stalls_for_bus: " << m_memBusBusy << endl;
> out << " memory_stalls_for_tfaw: " << m_memTfawBusy << endl;
> out << " memory_stalls_for_read_write_turnaround: " << m_memReadWriteBusy << endl;
> out << " memory_stalls_for_read_read_turnaround: " << m_memDataBusBusy << endl;
> out << " accesses_per_bank: ";
> for (int bank=0; bank < m_memBankCount.size(); bank++) {
> out << m_memBankCount[bank] << " ";
> //if ((bank % 8) == 7) out << " " << endl;
> }
> out << endl;
> out << endl;
378,379d470
< out << endl;
< out << endl;
381d471
<
416c506
< out << "miss_latency_" << CacheRequestType(i) << ": " << m_missLatencyHistograms[i] << endl;
---
> out << "miss_latency_" << RubyRequestType(i) << ": " << m_missLatencyHistograms[i] << endl;
503c593
< if (!PROFILE_ALL_INSTRUCTIONS) {
---
> if (!m_all_instructions) {
507c597
< if (PROFILE_ALL_INSTRUCTIONS) {
---
> if (m_all_instructions) {
553,555c643,645
< m_instructions_executed_at_start.setSize(RubyConfig::numberOfProcessors());
< m_cycles_executed_at_start.setSize(RubyConfig::numberOfProcessors());
< for (int i=0; i < RubyConfig::numberOfProcessors(); i++) {
---
> m_instructions_executed_at_start.setSize(RubySystem::getNumberOfSequencers());
> m_cycles_executed_at_start.setSize(RubySystem::getNumberOfSequencers());
> for (int i=0; i < RubySystem::getNumberOfSequencers(); i++) {
560,561c650,651
< m_instructions_executed_at_start[i] = g_system_ptr->getDriver()->getInstructionCount(i);
< m_cycles_executed_at_start[i] = g_system_ptr->getDriver()->getCycleCount(i);
---
> m_instructions_executed_at_start[i] = g_system_ptr->getInstructionCount(i);
> m_cycles_executed_at_start[i] = g_system_ptr->getCycleCount(i);
565,569c655,659
< m_perProcTotalMisses.setSize(RubyConfig::numberOfProcessors());
< m_perProcUserMisses.setSize(RubyConfig::numberOfProcessors());
< m_perProcSupervisorMisses.setSize(RubyConfig::numberOfProcessors());
< m_perProcStartTransaction.setSize(RubyConfig::numberOfProcessors());
< m_perProcEndTransaction.setSize(RubyConfig::numberOfProcessors());
---
> m_perProcTotalMisses.setSize(RubySystem::getNumberOfSequencers());
> m_perProcUserMisses.setSize(RubySystem::getNumberOfSequencers());
> m_perProcSupervisorMisses.setSize(RubySystem::getNumberOfSequencers());
> m_perProcStartTransaction.setSize(RubySystem::getNumberOfSequencers());
> m_perProcEndTransaction.setSize(RubySystem::getNumberOfSequencers());
571c661
< for(int i=0; i < RubyConfig::numberOfProcessors(); i++) {
---
> for(int i=0; i < RubySystem::getNumberOfSequencers(); i++) {
590,591c680,681
< m_delayedCyclesVCHistograms.setSize(NUMBER_OF_VIRTUAL_NETWORKS);
< for (int i = 0; i < NUMBER_OF_VIRTUAL_NETWORKS; i++) {
---
> m_delayedCyclesVCHistograms.setSize(RubySystem::getNetwork()->getNumberOfVirtualNetworks());
> for (int i = 0; i < RubySystem::getNetwork()->getNumberOfVirtualNetworks(); i++) {
658a749
> /*
677a769,771
> */
> //added by SS
> vector<string>::iterator it;
678a773,793
> for ( it=m_memory_control_names.begin() ; it < m_memory_control_names.end(); it++ ){
> m_memory_control_profilers[(*it).c_str()] -> m_memReq = 0;
> m_memory_control_profilers[(*it).c_str()] -> m_memBankBusy = 0;
> m_memory_control_profilers[(*it).c_str()] -> m_memBusBusy = 0;
> m_memory_control_profilers[(*it).c_str()] -> m_memTfawBusy = 0;
> m_memory_control_profilers[(*it).c_str()] -> m_memReadWriteBusy = 0;
> m_memory_control_profilers[(*it).c_str()] -> m_memDataBusBusy = 0;
> m_memory_control_profilers[(*it).c_str()] -> m_memRefresh = 0;
> m_memory_control_profilers[(*it).c_str()] -> m_memRead = 0;
> m_memory_control_profilers[(*it).c_str()] -> m_memWrite = 0;
> m_memory_control_profilers[(*it).c_str()] -> m_memWaitCycles = 0;
> m_memory_control_profilers[(*it).c_str()] -> m_memInputQ = 0;
> m_memory_control_profilers[(*it).c_str()] -> m_memBankQ = 0;
> m_memory_control_profilers[(*it).c_str()] -> m_memArbWait = 0;
> m_memory_control_profilers[(*it).c_str()] -> m_memRandBusy = 0;
> m_memory_control_profilers[(*it).c_str()] -> m_memNotOld = 0;
>
> for (int bank=0; bank < m_memory_control_profilers[(*it).c_str()] -> m_memBankCount.size(); bank++) {
> m_memory_control_profilers[(*it).c_str()] -> m_memBankCount[bank] = 0;
> }
> }
710c825
< last_time = m_conflicting_map_ptr->lookup(addr);
---
> Time last_time = m_conflicting_map_ptr->lookup(addr);
758,759c873,874
< // NOTE: Unless PROFILE_HOT_LINES or PROFILE_ALL_INSTRUCTIONS are enabled, nothing will be profiled by the AddressProfiler
< m_address_profiler_ptr->addTraceSample(msg.getAddress(), msg.getProgramCounter(), msg.getType(), msg.getAccessMode(), id, false);
---
> // NOTE: Unless PROFILE_HOT_LINES or RubyConfig::getProfileAllInstructions() are enabled, nothing will be profiled by the AddressProfiler
> m_address_profiler_ptr->addTraceSample(msg.getLineAddress(), msg.getProgramCounter(), msg.getType(), msg.getAccessMode(), id, false);
855c970
< void Profiler::missLatency(Time t, CacheRequestType type, GenericMachineType respondingMach)
---
> void Profiler::missLatency(Time t, RubyRequestType type)
858a974
> /*
862a979
> */
876c993
< void Profiler::profileTransition(const string& component, NodeID id, NodeID version, Address addr,
---
> void Profiler::profileTransition(const string& component, NodeID version, Address addr,
890d1006
< (* debug_cout_ptr) << setw(ID_SPACES) << id << " ";
894d1009
< for (int i=0; i < RubyConfig::numberOfProcessors(); i++) {
896,905c1011,1016
< if (i == id) {
< (* debug_cout_ptr).flags(ios::right);
< (* debug_cout_ptr) << setw(STATE_SPACES) << state;
< (* debug_cout_ptr) << ">";
< (* debug_cout_ptr).flags(ios::left);
< (* debug_cout_ptr) << setw(STATE_SPACES) << next_state;
< } else {
< // cout << setw(STATE_SPACES) << " " << " " << setw(STATE_SPACES) << " ";
< }
< }
---
> (* debug_cout_ptr).flags(ios::right);
> (* debug_cout_ptr) << setw(STATE_SPACES) << state;
> (* debug_cout_ptr) << ">";
> (* debug_cout_ptr).flags(ios::left);
> (* debug_cout_ptr) << setw(STATE_SPACES) << next_state;
>
952,972d1062
< // For MemoryControl:
< void Profiler::profileMemReq(int bank) {
< m_memReq++;
< m_memBankCount[bank]++;
< }
<
< void Profiler::profileMemBankBusy() { m_memBankBusy++; }
< void Profiler::profileMemBusBusy() { m_memBusBusy++; }
< void Profiler::profileMemReadWriteBusy() { m_memReadWriteBusy++; }
< void Profiler::profileMemDataBusBusy() { m_memDataBusBusy++; }
< void Profiler::profileMemTfawBusy() { m_memTfawBusy++; }
< void Profiler::profileMemRefresh() { m_memRefresh++; }
< void Profiler::profileMemRead() { m_memRead++; }
< void Profiler::profileMemWrite() { m_memWrite++; }
< void Profiler::profileMemWaitCycles(int cycles) { m_memWaitCycles += cycles; }
< void Profiler::profileMemInputQ(int cycles) { m_memInputQ += cycles; }
< void Profiler::profileMemBankQ(int cycles) { m_memBankQ += cycles; }
< void Profiler::profileMemArbWait(int cycles) { m_memArbWait += cycles; }
< void Profiler::profileMemRandBusy() { m_memRandBusy++; }
< void Profiler::profileMemNotOld() { m_memNotOld++; }
<
976,977c1066,1067
< for(int i=0; i < RubyConfig::numberOfProcessors(); i++) {
< sum += (g_system_ptr->getDriver()->getInstructionCount(i) - m_instructions_executed_at_start[i]);
---
> for(int i=0; i < RubySystem::getNumberOfSequencers(); i++) {
> sum += (g_system_ptr->getInstructionCount(i) - m_instructions_executed_at_start[i]);
1016a1107,1154
> void Profiler::rubyWatch(int id){
> int rn_g1 = 0;//SIMICS_get_register_number(id, "g1");
> uint64 tr = 0;//SIMICS_read_register(id, rn_g1);
> Address watch_address = Address(tr);
> const int ID_SPACES = 3;
> const int TIME_SPACES = 7;
>
> (* debug_cout_ptr).flags(ios::right);
> (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
> (* debug_cout_ptr) << setw(ID_SPACES) << id << " "
> << "RUBY WATCH "
> << watch_address
> << endl;
>
> if(!m_watch_address_list_ptr->exist(watch_address)){
> m_watch_address_list_ptr->add(watch_address, 1);
> }
> }
>
> bool Profiler::watchAddress(Address addr){
> if (m_watch_address_list_ptr->exist(addr))
> return true;
> else
> return false;
> }
>
> // For MemoryControl:
> void Profiler::profileMemReq(string name, int bank) {
> // printf("name is %s", name.c_str());
> assert(m_memory_control_profilers.count(name) == 1);
> m_memory_control_profilers[name] -> m_memReq++;
> m_memory_control_profilers[name] -> m_memBankCount[bank]++;
> }
> void Profiler::profileMemBankBusy(string name) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memBankBusy++; }
> void Profiler::profileMemBusBusy(string name) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memBusBusy++; }
> void Profiler::profileMemReadWriteBusy(string name) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memReadWriteBusy++; }
> void Profiler::profileMemDataBusBusy(string name) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memDataBusBusy++; }
> void Profiler::profileMemTfawBusy(string name) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memTfawBusy++; }
> void Profiler::profileMemRefresh(string name) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memRefresh++; }
> void Profiler::profileMemRead(string name) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memRead++; }
> void Profiler::profileMemWrite(string name) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memWrite++; }
> void Profiler::profileMemWaitCycles(string name, int cycles) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memWaitCycles += cycles; }
> void Profiler::profileMemInputQ(string name, int cycles) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memInputQ += cycles; }
> void Profiler::profileMemBankQ(string name, int cycles) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memBankQ += cycles; }
> void Profiler::profileMemArbWait(string name, int cycles) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memArbWait += cycles; }
> void Profiler::profileMemRandBusy(string name) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memRandBusy++; }
> void Profiler::profileMemNotOld(string name) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memNotOld++; }
>
< #include "mem/ruby/common/Driver.hh"
76c75
< Profiler::Profiler()
---
> Profiler::Profiler(const string & name)
78a78
> m_name = name;
84a85,88
> m_inst_profiler_ptr = NULL;
> m_address_profiler_ptr = NULL;
>
> /*
87c91
< if (PROFILE_ALL_INSTRUCTIONS) {
---
> if (m_all_instructions) {
90c94
<
---
> */
96a101,102
> //changed by SS
> /*
119,120c125
<
< clearStats();
---
> */
135a141,205
> void Profiler::init(const vector<string> & argv, vector<string> memory_control_names)
> {
> // added by SS
> vector<string>::iterator it;
> memory_control_profiler* mcp;
> m_memory_control_names = memory_control_names;
> // printf ( "Here in Profiler::init \n");
> for ( it=memory_control_names.begin() ; it < memory_control_names.end(); it++ ){
> // printf ( "Here in Profiler::init memory control name %s \n", (*it).c_str());
> mcp = new memory_control_profiler;
> mcp->m_memReq = 0;
> mcp->m_memBankBusy = 0;
> mcp->m_memBusBusy = 0;
> mcp->m_memReadWriteBusy = 0;
> mcp->m_memDataBusBusy = 0;
> mcp->m_memTfawBusy = 0;
> mcp->m_memRefresh = 0;
> mcp->m_memRead = 0;
> mcp->m_memWrite = 0;
> mcp->m_memWaitCycles = 0;
> mcp->m_memInputQ = 0;
> mcp->m_memBankQ = 0;
> mcp->m_memArbWait = 0;
> mcp->m_memRandBusy = 0;
> mcp->m_memNotOld = 0;
>
> mcp->m_banks_per_rank = RubySystem::getMemoryControl((*it).c_str())->getBanksPerRank();
> mcp->m_ranks_per_dimm = RubySystem::getMemoryControl((*it).c_str())->getRanksPerDimm();
> mcp->m_dimms_per_channel = RubySystem::getMemoryControl((*it).c_str())->getDimmsPerChannel();
>
> int totalBanks = mcp->m_banks_per_rank
> * mcp->m_ranks_per_dimm
> * mcp->m_dimms_per_channel;
>
> mcp->m_memBankCount.setSize(totalBanks);
>
> m_memory_control_profilers [(*it).c_str()] = mcp;
> }
>
> clearStats();
> m_hot_lines = false;
> m_all_instructions = false;
>
> for (size_t i=0; i<argv.size(); i+=2) {
> if ( argv[i] == "hot_lines") {
> m_hot_lines = (argv[i+1]=="true");
> } else if ( argv[i] == "all_instructions") {
> m_all_instructions = (argv[i+1]=="true");
> }else {
> cerr << "WARNING: Profiler: Unkown configuration parameter: " << argv[i] << endl;
> assert(false);
> }
> }
>
> m_address_profiler_ptr = new AddressProfiler;
> m_address_profiler_ptr -> setHotLines(m_hot_lines);
> m_address_profiler_ptr -> setAllInstructions(m_all_instructions);
>
> if (m_all_instructions) {
> m_inst_profiler_ptr = new AddressProfiler;
> m_inst_profiler_ptr -> setHotLines(m_hot_lines);
> m_inst_profiler_ptr -> setAllInstructions(m_all_instructions);
> }
> }
>
141c211
< perProcInstructionCount.setSize(RubyConfig::numberOfProcessors());
---
> perProcInstructionCount.setSize(RubySystem::getNumberOfSequencers());
144c214
< perProcCycleCount.setSize(RubyConfig::numberOfProcessors());
---
> perProcCycleCount.setSize(RubySystem::getNumberOfSequencers());
146,148c216,218
< for(int i=0; i < RubyConfig::numberOfProcessors(); i++) {
< perProcInstructionCount[i] = g_system_ptr->getDriver()->getInstructionCount(i) - m_instructions_executed_at_start[i] + 1;
< perProcCycleCount[i] = g_system_ptr->getDriver()->getCycleCount(i) - m_cycles_executed_at_start[i] + 1;
---
> for(int i=0; i < RubySystem::getNumberOfSequencers(); i++) {
> perProcInstructionCount[i] = g_system_ptr->getInstructionCount(i) - m_instructions_executed_at_start[i] + 1;
> perProcCycleCount[i] = g_system_ptr->getCycleCount(i) - m_cycles_executed_at_start[i] + 1;
154c224
< integer_t cycles_executed = perProcCycleCount.sum();
---
> integer_t simics_cycles_executed = perProcCycleCount.sum();
161c231
< (*m_periodic_output_file_ptr) << "cycles_executed: " << cycles_executed << " " << perProcCycleCount << endl;
---
> (*m_periodic_output_file_ptr) << "simics_cycles_executed: " << simics_cycles_executed << " " << perProcCycleCount << endl;
175c245
< if (PROFILE_ALL_INSTRUCTIONS) {
---
> if (m_all_instructions) {
280,283c350,353
< perProcInstructionCount.setSize(RubyConfig::numberOfProcessors());
< perProcCycleCount.setSize(RubyConfig::numberOfProcessors());
< perProcCPI.setSize(RubyConfig::numberOfProcessors());
< perProcMissesPerInsn.setSize(RubyConfig::numberOfProcessors());
---
> perProcInstructionCount.setSize(RubySystem::getNumberOfSequencers());
> perProcCycleCount.setSize(RubySystem::getNumberOfSequencers());
> perProcCPI.setSize(RubySystem::getNumberOfSequencers());
> perProcMissesPerInsn.setSize(RubySystem::getNumberOfSequencers());
285,287c355,357
< perProcInsnPerTrans.setSize(RubyConfig::numberOfProcessors());
< perProcCyclesPerTrans.setSize(RubyConfig::numberOfProcessors());
< perProcMissesPerTrans.setSize(RubyConfig::numberOfProcessors());
---
> perProcInsnPerTrans.setSize(RubySystem::getNumberOfSequencers());
> perProcCyclesPerTrans.setSize(RubySystem::getNumberOfSequencers());
> perProcMissesPerTrans.setSize(RubySystem::getNumberOfSequencers());
289,291c359,361
< for(int i=0; i < RubyConfig::numberOfProcessors(); i++) {
< perProcInstructionCount[i] = g_system_ptr->getDriver()->getInstructionCount(i) - m_instructions_executed_at_start[i] + 1;
< perProcCycleCount[i] = g_system_ptr->getDriver()->getCycleCount(i) - m_cycles_executed_at_start[i] + 1;
---
> for(int i=0; i < RubySystem::getNumberOfSequencers(); i++) {
> perProcInstructionCount[i] = g_system_ptr->getInstructionCount(i) - m_instructions_executed_at_start[i] + 1;
> perProcCycleCount[i] = g_system_ptr->getCycleCount(i) - m_cycles_executed_at_start[i] + 1;
312c382
< integer_t cycles_executed = perProcCycleCount.sum();
---
> integer_t simics_cycles_executed = perProcCycleCount.sum();
317c387
< double cycles_per_transaction = (transactions_ended != 0) ? (RubyConfig::numberOfProcessors() * double(ruby_cycles)) / double(transactions_ended) : 0;
---
> double cycles_per_transaction = (transactions_ended != 0) ? (RubySystem::getNumberOfSequencers() * double(ruby_cycles)) / double(transactions_ended) : 0;
326,327c396,397
< out << "cycles_executed: " << cycles_executed << " " << perProcCycleCount << endl;
< out << "cycles_per_instruction: " << (RubyConfig::numberOfProcessors()*double(ruby_cycles))/double(instruction_executed) << " " << perProcCPI << endl;
---
> out << "ruby_cycles_executed: " << simics_cycles_executed << " " << perProcCycleCount << endl;
> out << "cycles_per_instruction: " << (RubySystem::getNumberOfSequencers()*double(ruby_cycles))/double(instruction_executed) << " " << perProcCPI << endl;
344,376c414,469
< if (m_memReq || m_memRefresh) { // if there's a memory controller at all
< long long int total_stalls = m_memInputQ + m_memBankQ + m_memWaitCycles;
< double stallsPerReq = total_stalls * 1.0 / m_memReq;
< out << "Memory control:" << endl;
< out << " memory_total_requests: " << m_memReq << endl; // does not include refreshes
< out << " memory_reads: " << m_memRead << endl;
< out << " memory_writes: " << m_memWrite << endl;
< out << " memory_refreshes: " << m_memRefresh << endl;
< out << " memory_total_request_delays: " << total_stalls << endl;
< out << " memory_delays_per_request: " << stallsPerReq << endl;
< out << " memory_delays_in_input_queue: " << m_memInputQ << endl;
< out << " memory_delays_behind_head_of_bank_queue: " << m_memBankQ << endl;
< out << " memory_delays_stalled_at_head_of_bank_queue: " << m_memWaitCycles << endl;
< // Note: The following "memory stalls" entries are a breakdown of the
< // cycles which already showed up in m_memWaitCycles. The order is
< // significant; it is the priority of attributing the cycles.
< // For example, bank_busy is before arbitration because if the bank was
< // busy, we didn't even check arbitration.
< // Note: "not old enough" means that since we grouped waiting heads-of-queues
< // into batches to avoid starvation, a request in a newer batch
< // didn't try to arbitrate yet because there are older requests waiting.
< out << " memory_stalls_for_bank_busy: " << m_memBankBusy << endl;
< out << " memory_stalls_for_random_busy: " << m_memRandBusy << endl;
< out << " memory_stalls_for_anti_starvation: " << m_memNotOld << endl;
< out << " memory_stalls_for_arbitration: " << m_memArbWait << endl;
< out << " memory_stalls_for_bus: " << m_memBusBusy << endl;
< out << " memory_stalls_for_tfaw: " << m_memTfawBusy << endl;
< out << " memory_stalls_for_read_write_turnaround: " << m_memReadWriteBusy << endl;
< out << " memory_stalls_for_read_read_turnaround: " << m_memDataBusBusy << endl;
< out << " accesses_per_bank: ";
< for (int bank=0; bank < m_memBankCount.size(); bank++) {
< out << m_memBankCount[bank] << " ";
< //if ((bank % 8) == 7) out << " " << endl;
---
> vector<string>::iterator it;
>
> for ( it=m_memory_control_names.begin() ; it < m_memory_control_names.end(); it++ ){
> long long int m_memReq = m_memory_control_profilers[(*it).c_str()] -> m_memReq;
> long long int m_memRefresh = m_memory_control_profilers[(*it).c_str()] -> m_memRefresh;
> long long int m_memInputQ = m_memory_control_profilers[(*it).c_str()] -> m_memInputQ;
> long long int m_memBankQ = m_memory_control_profilers[(*it).c_str()] -> m_memBankQ;
> long long int m_memWaitCycles = m_memory_control_profilers[(*it).c_str()] -> m_memWaitCycles;
> long long int m_memRead = m_memory_control_profilers[(*it).c_str()] -> m_memRead;
> long long int m_memWrite = m_memory_control_profilers[(*it).c_str()] -> m_memWrite;
> long long int m_memBankBusy = m_memory_control_profilers[(*it).c_str()] -> m_memBankBusy;
> long long int m_memRandBusy = m_memory_control_profilers[(*it).c_str()] -> m_memRandBusy;
> long long int m_memNotOld = m_memory_control_profilers[(*it).c_str()] -> m_memNotOld;
> long long int m_memArbWait = m_memory_control_profilers[(*it).c_str()] -> m_memArbWait;
> long long int m_memBusBusy = m_memory_control_profilers[(*it).c_str()] -> m_memBusBusy;
> long long int m_memTfawBusy = m_memory_control_profilers[(*it).c_str()] -> m_memTfawBusy;
> long long int m_memReadWriteBusy = m_memory_control_profilers[(*it).c_str()] -> m_memReadWriteBusy;
> long long int m_memDataBusBusy = m_memory_control_profilers[(*it).c_str()] -> m_memDataBusBusy;
> Vector<long long int> m_memBankCount = m_memory_control_profilers[(*it).c_str()] -> m_memBankCount;
>
> if (m_memReq || m_memRefresh) { // if there's a memory controller at all
> long long int total_stalls = m_memInputQ + m_memBankQ + m_memWaitCycles;
> double stallsPerReq = total_stalls * 1.0 / m_memReq;
> out << "Memory control:" << endl;
> out << " memory_total_requests: " << m_memReq << endl; // does not include refreshes
> out << " memory_reads: " << m_memRead << endl;
> out << " memory_writes: " << m_memWrite << endl;
> out << " memory_refreshes: " << m_memRefresh << endl;
> out << " memory_total_request_delays: " << total_stalls << endl;
> out << " memory_delays_per_request: " << stallsPerReq << endl;
> out << " memory_delays_in_input_queue: " << m_memInputQ << endl;
> out << " memory_delays_behind_head_of_bank_queue: " << m_memBankQ << endl;
> out << " memory_delays_stalled_at_head_of_bank_queue: " << m_memWaitCycles << endl;
> // Note: The following "memory stalls" entries are a breakdown of the
> // cycles which already showed up in m_memWaitCycles. The order is
> // significant; it is the priority of attributing the cycles.
> // For example, bank_busy is before arbitration because if the bank was
> // busy, we didn't even check arbitration.
> // Note: "not old enough" means that since we grouped waiting heads-of-queues
> // into batches to avoid starvation, a request in a newer batch
> // didn't try to arbitrate yet because there are older requests waiting.
> out << " memory_stalls_for_bank_busy: " << m_memBankBusy << endl;
> out << " memory_stalls_for_random_busy: " << m_memRandBusy << endl;
> out << " memory_stalls_for_anti_starvation: " << m_memNotOld << endl;
> out << " memory_stalls_for_arbitration: " << m_memArbWait << endl;
> out << " memory_stalls_for_bus: " << m_memBusBusy << endl;
> out << " memory_stalls_for_tfaw: " << m_memTfawBusy << endl;
> out << " memory_stalls_for_read_write_turnaround: " << m_memReadWriteBusy << endl;
> out << " memory_stalls_for_read_read_turnaround: " << m_memDataBusBusy << endl;
> out << " accesses_per_bank: ";
> for (int bank=0; bank < m_memBankCount.size(); bank++) {
> out << m_memBankCount[bank] << " ";
> //if ((bank % 8) == 7) out << " " << endl;
> }
> out << endl;
> out << endl;
378,379d470
< out << endl;
< out << endl;
381d471
<
416c506
< out << "miss_latency_" << CacheRequestType(i) << ": " << m_missLatencyHistograms[i] << endl;
---
> out << "miss_latency_" << RubyRequestType(i) << ": " << m_missLatencyHistograms[i] << endl;
503c593
< if (!PROFILE_ALL_INSTRUCTIONS) {
---
> if (!m_all_instructions) {
507c597
< if (PROFILE_ALL_INSTRUCTIONS) {
---
> if (m_all_instructions) {
553,555c643,645
< m_instructions_executed_at_start.setSize(RubyConfig::numberOfProcessors());
< m_cycles_executed_at_start.setSize(RubyConfig::numberOfProcessors());
< for (int i=0; i < RubyConfig::numberOfProcessors(); i++) {
---
> m_instructions_executed_at_start.setSize(RubySystem::getNumberOfSequencers());
> m_cycles_executed_at_start.setSize(RubySystem::getNumberOfSequencers());
> for (int i=0; i < RubySystem::getNumberOfSequencers(); i++) {
560,561c650,651
< m_instructions_executed_at_start[i] = g_system_ptr->getDriver()->getInstructionCount(i);
< m_cycles_executed_at_start[i] = g_system_ptr->getDriver()->getCycleCount(i);
---
> m_instructions_executed_at_start[i] = g_system_ptr->getInstructionCount(i);
> m_cycles_executed_at_start[i] = g_system_ptr->getCycleCount(i);
565,569c655,659
< m_perProcTotalMisses.setSize(RubyConfig::numberOfProcessors());
< m_perProcUserMisses.setSize(RubyConfig::numberOfProcessors());
< m_perProcSupervisorMisses.setSize(RubyConfig::numberOfProcessors());
< m_perProcStartTransaction.setSize(RubyConfig::numberOfProcessors());
< m_perProcEndTransaction.setSize(RubyConfig::numberOfProcessors());
---
> m_perProcTotalMisses.setSize(RubySystem::getNumberOfSequencers());
> m_perProcUserMisses.setSize(RubySystem::getNumberOfSequencers());
> m_perProcSupervisorMisses.setSize(RubySystem::getNumberOfSequencers());
> m_perProcStartTransaction.setSize(RubySystem::getNumberOfSequencers());
> m_perProcEndTransaction.setSize(RubySystem::getNumberOfSequencers());
571c661
< for(int i=0; i < RubyConfig::numberOfProcessors(); i++) {
---
> for(int i=0; i < RubySystem::getNumberOfSequencers(); i++) {
590,591c680,681
< m_delayedCyclesVCHistograms.setSize(NUMBER_OF_VIRTUAL_NETWORKS);
< for (int i = 0; i < NUMBER_OF_VIRTUAL_NETWORKS; i++) {
---
> m_delayedCyclesVCHistograms.setSize(RubySystem::getNetwork()->getNumberOfVirtualNetworks());
> for (int i = 0; i < RubySystem::getNetwork()->getNumberOfVirtualNetworks(); i++) {
658a749
> /*
677a769,771
> */
> //added by SS
> vector<string>::iterator it;
678a773,793
> for ( it=m_memory_control_names.begin() ; it < m_memory_control_names.end(); it++ ){
> m_memory_control_profilers[(*it).c_str()] -> m_memReq = 0;
> m_memory_control_profilers[(*it).c_str()] -> m_memBankBusy = 0;
> m_memory_control_profilers[(*it).c_str()] -> m_memBusBusy = 0;
> m_memory_control_profilers[(*it).c_str()] -> m_memTfawBusy = 0;
> m_memory_control_profilers[(*it).c_str()] -> m_memReadWriteBusy = 0;
> m_memory_control_profilers[(*it).c_str()] -> m_memDataBusBusy = 0;
> m_memory_control_profilers[(*it).c_str()] -> m_memRefresh = 0;
> m_memory_control_profilers[(*it).c_str()] -> m_memRead = 0;
> m_memory_control_profilers[(*it).c_str()] -> m_memWrite = 0;
> m_memory_control_profilers[(*it).c_str()] -> m_memWaitCycles = 0;
> m_memory_control_profilers[(*it).c_str()] -> m_memInputQ = 0;
> m_memory_control_profilers[(*it).c_str()] -> m_memBankQ = 0;
> m_memory_control_profilers[(*it).c_str()] -> m_memArbWait = 0;
> m_memory_control_profilers[(*it).c_str()] -> m_memRandBusy = 0;
> m_memory_control_profilers[(*it).c_str()] -> m_memNotOld = 0;
>
> for (int bank=0; bank < m_memory_control_profilers[(*it).c_str()] -> m_memBankCount.size(); bank++) {
> m_memory_control_profilers[(*it).c_str()] -> m_memBankCount[bank] = 0;
> }
> }
710c825
< last_time = m_conflicting_map_ptr->lookup(addr);
---
> Time last_time = m_conflicting_map_ptr->lookup(addr);
758,759c873,874
< // NOTE: Unless PROFILE_HOT_LINES or PROFILE_ALL_INSTRUCTIONS are enabled, nothing will be profiled by the AddressProfiler
< m_address_profiler_ptr->addTraceSample(msg.getAddress(), msg.getProgramCounter(), msg.getType(), msg.getAccessMode(), id, false);
---
> // NOTE: Unless PROFILE_HOT_LINES or RubyConfig::getProfileAllInstructions() are enabled, nothing will be profiled by the AddressProfiler
> m_address_profiler_ptr->addTraceSample(msg.getLineAddress(), msg.getProgramCounter(), msg.getType(), msg.getAccessMode(), id, false);
855c970
< void Profiler::missLatency(Time t, CacheRequestType type, GenericMachineType respondingMach)
---
> void Profiler::missLatency(Time t, RubyRequestType type)
858a974
> /*
862a979
> */
876c993
< void Profiler::profileTransition(const string& component, NodeID id, NodeID version, Address addr,
---
> void Profiler::profileTransition(const string& component, NodeID version, Address addr,
890d1006
< (* debug_cout_ptr) << setw(ID_SPACES) << id << " ";
894d1009
< for (int i=0; i < RubyConfig::numberOfProcessors(); i++) {
896,905c1011,1016
< if (i == id) {
< (* debug_cout_ptr).flags(ios::right);
< (* debug_cout_ptr) << setw(STATE_SPACES) << state;
< (* debug_cout_ptr) << ">";
< (* debug_cout_ptr).flags(ios::left);
< (* debug_cout_ptr) << setw(STATE_SPACES) << next_state;
< } else {
< // cout << setw(STATE_SPACES) << " " << " " << setw(STATE_SPACES) << " ";
< }
< }
---
> (* debug_cout_ptr).flags(ios::right);
> (* debug_cout_ptr) << setw(STATE_SPACES) << state;
> (* debug_cout_ptr) << ">";
> (* debug_cout_ptr).flags(ios::left);
> (* debug_cout_ptr) << setw(STATE_SPACES) << next_state;
>
952,972d1062
< // For MemoryControl:
< void Profiler::profileMemReq(int bank) {
< m_memReq++;
< m_memBankCount[bank]++;
< }
<
< void Profiler::profileMemBankBusy() { m_memBankBusy++; }
< void Profiler::profileMemBusBusy() { m_memBusBusy++; }
< void Profiler::profileMemReadWriteBusy() { m_memReadWriteBusy++; }
< void Profiler::profileMemDataBusBusy() { m_memDataBusBusy++; }
< void Profiler::profileMemTfawBusy() { m_memTfawBusy++; }
< void Profiler::profileMemRefresh() { m_memRefresh++; }
< void Profiler::profileMemRead() { m_memRead++; }
< void Profiler::profileMemWrite() { m_memWrite++; }
< void Profiler::profileMemWaitCycles(int cycles) { m_memWaitCycles += cycles; }
< void Profiler::profileMemInputQ(int cycles) { m_memInputQ += cycles; }
< void Profiler::profileMemBankQ(int cycles) { m_memBankQ += cycles; }
< void Profiler::profileMemArbWait(int cycles) { m_memArbWait += cycles; }
< void Profiler::profileMemRandBusy() { m_memRandBusy++; }
< void Profiler::profileMemNotOld() { m_memNotOld++; }
<
976,977c1066,1067
< for(int i=0; i < RubyConfig::numberOfProcessors(); i++) {
< sum += (g_system_ptr->getDriver()->getInstructionCount(i) - m_instructions_executed_at_start[i]);
---
> for(int i=0; i < RubySystem::getNumberOfSequencers(); i++) {
> sum += (g_system_ptr->getInstructionCount(i) - m_instructions_executed_at_start[i]);
1016a1107,1154
> void Profiler::rubyWatch(int id){
> int rn_g1 = 0;//SIMICS_get_register_number(id, "g1");
> uint64 tr = 0;//SIMICS_read_register(id, rn_g1);
> Address watch_address = Address(tr);
> const int ID_SPACES = 3;
> const int TIME_SPACES = 7;
>
> (* debug_cout_ptr).flags(ios::right);
> (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
> (* debug_cout_ptr) << setw(ID_SPACES) << id << " "
> << "RUBY WATCH "
> << watch_address
> << endl;
>
> if(!m_watch_address_list_ptr->exist(watch_address)){
> m_watch_address_list_ptr->add(watch_address, 1);
> }
> }
>
> bool Profiler::watchAddress(Address addr){
> if (m_watch_address_list_ptr->exist(addr))
> return true;
> else
> return false;
> }
>
> // For MemoryControl:
> void Profiler::profileMemReq(string name, int bank) {
> // printf("name is %s", name.c_str());
> assert(m_memory_control_profilers.count(name) == 1);
> m_memory_control_profilers[name] -> m_memReq++;
> m_memory_control_profilers[name] -> m_memBankCount[bank]++;
> }
> void Profiler::profileMemBankBusy(string name) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memBankBusy++; }
> void Profiler::profileMemBusBusy(string name) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memBusBusy++; }
> void Profiler::profileMemReadWriteBusy(string name) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memReadWriteBusy++; }
> void Profiler::profileMemDataBusBusy(string name) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memDataBusBusy++; }
> void Profiler::profileMemTfawBusy(string name) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memTfawBusy++; }
> void Profiler::profileMemRefresh(string name) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memRefresh++; }
> void Profiler::profileMemRead(string name) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memRead++; }
> void Profiler::profileMemWrite(string name) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memWrite++; }
> void Profiler::profileMemWaitCycles(string name, int cycles) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memWaitCycles += cycles; }
> void Profiler::profileMemInputQ(string name, int cycles) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memInputQ += cycles; }
> void Profiler::profileMemBankQ(string name, int cycles) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memBankQ += cycles; }
> void Profiler::profileMemArbWait(string name, int cycles) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memArbWait += cycles; }
> void Profiler::profileMemRandBusy(string name) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memRandBusy++; }
> void Profiler::profileMemNotOld(string name) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memNotOld++; }
>