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< // #include "TransactionInterfaceManager.hh"
< #include "interface.hh"
< //#include "XactVisualizer.hh" //gem5:Arka for decomissioning log_tm
< //#include "XactProfiler.hh" //gem5:Arka for decomissioning log_tm
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< // extern "C" {
< // #include "Rock.hh"
< // }
<
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< extern std::ostream * xact_cout_ptr;
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< //m_xact_profiler_ptr = new XactProfiler; //gem5:Arka for decomissioning og log_tm
<
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< m_xact_visualizer_ptr = &cout;
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< //---- begin XACT_MEM code
< m_xactExceptionMap_ptr = new Map<int, int>;
< m_procsInXactMap_ptr = new Map<int, int>;
< m_abortIDMap_ptr = new Map<int, int>;
< m_commitIDMap_ptr = new Map<int, int>;
< m_xactRetryIDMap_ptr = new Map<int, int>;
< m_xactCyclesIDMap_ptr = new Map<int, int>;
< m_xactReadSetIDMap_ptr = new Map<int, int>;
< m_xactWriteSetIDMap_ptr = new Map<int, int>;
< m_xactLoadMissIDMap_ptr = new Map<int, int>;
< m_xactStoreMissIDMap_ptr = new Map<int, int>;
< m_xactInstrCountIDMap_ptr = new Map<int, integer_t>;
< m_abortPCMap_ptr = new Map<Address, int>;
< m_abortAddressMap_ptr = new Map<Address, int>;
< m_nackXIDMap_ptr = new Map<int, int>;
< m_nackXIDPairMap_ptr = new Map<int, Map<int, int> * >;
< m_nackPCMap_ptr = new Map<Address, int>;
< m_watch_address_list_ptr = new Map<Address, int>;
< m_readSetMatch_ptr = new Map<Address, int>;
< m_readSetNoMatch_ptr = new Map<Address, int>;
< m_writeSetMatch_ptr = new Map<Address, int>;
< m_writeSetNoMatch_ptr = new Map<Address, int>;
< m_xactReadFilterBitsSetOnCommit = new Map<int, Histogram>;
< m_xactReadFilterBitsSetOnAbort = new Map<int, Histogram>;
< m_xactWriteFilterBitsSetOnCommit = new Map<int, Histogram>;
< m_xactWriteFilterBitsSetOnAbort = new Map<int, Histogram>;
< //---- end XACT_MEM code
<
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< //delete m_xact_profiler_ptr; //gem5:Arka for decomissioning of log_tm
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< integer_t simics_cycles_executed = perProcCycleCount.sum();
---
> integer_t cycles_executed = perProcCycleCount.sum();
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< (*m_periodic_output_file_ptr) << "simics_cycles_executed: " << simics_cycles_executed << " " << perProcCycleCount << endl;
---
> (*m_periodic_output_file_ptr) << "cycles_executed: " << cycles_executed << " " << perProcCycleCount << endl;
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< integer_t simics_cycles_executed = perProcCycleCount.sum();
---
> integer_t cycles_executed = perProcCycleCount.sum();
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< out << "simics_cycles_executed: " << simics_cycles_executed << " " << perProcCycleCount << endl;
---
> out << "cycles_executed: " << cycles_executed << " " << perProcCycleCount << endl;
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< if (XACT_MEMORY){
< // Transactional Memory stats
< out << "Transactional Memory Stats:" << endl;
< out << "------- xact --------" << endl;
< out << "xact_size_dist: " << m_xactSizes << endl;
< out << "xact_instr_count: " << m_xactInstrCount << endl;
< out << "xact_time_dist: " << m_xactCycles << endl;
< out << "xact_log_size_dist: " << m_xactLogs << endl;
< out << "xact_read_set_size_dist: " << m_xactReads << endl;
< out << "xact_write_set_size_dist: " << m_xactWrites << endl;
< out << "xact_overflow_read_lines_dist: " << m_xactOverflowReads << endl;
< out << "xact_overflow_write_lines_dist: " << m_xactOverflowWrites << endl;
< out << "xact_overflow_read_set_size_dist: " << m_xactOverflowTotalReads << endl;
< out << "xact_overflow_write_set_size_dist: " << m_xactOverflowTotalWrites << endl;
< out << "xact_miss_load_dist: " << m_xactLoadMisses << endl;
< out << "xact_miss_store_dist: " << m_xactStoreMisses << endl;
< out << "xact_nacked: " << m_xactNacked << endl;
< out << "xact_retries: " << m_xactRetries << endl;
< out << "xact_abort_delays: " << m_abortDelays << endl;
< out << "xact_aborts: " << m_transactionAborts << endl;
< if (ATMTP_ENABLED) {
< out << "xact_log_overflows: " << m_transactionLogOverflows << endl;
< out << "xact_cache_overflows: " << m_transactionCacheOverflows << endl;
< out << "xact_unsup_inst_aborts: " << m_transactionUnsupInsts << endl;
< out << "xact_save_rest_aborts: " << m_transactionSaveRestAborts << endl;
< }
< out << "xact_writebacks: " << m_transWBs << endl;
< out << "xact_extra_wbs: " << m_extraWBs << endl;
< out << "xact_handler_startup_delay: " << m_abortStarupDelay << endl;
< out << "xact_handler_per_block_delay: " << m_abortPerBlockDelay << endl;
< out << "xact_inferred_aborts: " << m_inferredAborts << endl;
< //out << "xact_histogram: " << m_procsInXact << endl;
<
< if (!short_stats) {
< Vector<int> nackedXIDKeys = m_nackXIDMap_ptr->keys();
< nackedXIDKeys.sortVector();
< out << endl;
< int total_nacks = 0;
< out << "------- xact Nacks by XID --------" << endl;
< for(int i=0; i<nackedXIDKeys.size(); i++) {
< int key = nackedXIDKeys[i];
< int count = m_nackXIDMap_ptr->lookup(key);
< total_nacks += count;
< out << "xact " << key << " "
< << setw(6) << dec << count
< << endl;
< }
< out << "Total Nacks: " << total_nacks << endl;
< out << "---------------" << endl;
< out << endl;
<
< // Print XID Nack Pairs
< Vector<int> nackedXIDPairKeys = m_nackXIDPairMap_ptr->keys();
< nackedXIDPairKeys.sortVector();
< out << endl;
< total_nacks = 0;
< out << "------- xact Nacks by XID Pairs --------" << endl;
< for(int i=0; i<nackedXIDPairKeys.size(); i++) {
< int key = nackedXIDPairKeys[i];
< Map<int, int> * my_map = m_nackXIDPairMap_ptr->lookup(key);
< Vector<int> my_keys = my_map->keys();
< my_keys.sortVector();
< for(int j=0; j<my_keys.size(); j++){
< int nid = my_keys[j];
< int count = my_map->lookup(nid);
< total_nacks += count;
< out << "xact " << key << " nacked by xact " << nid << " "
< << setw(6) << dec << count
< << endl;
< }
< }
< out << "Total Nacks: " << total_nacks << endl;
< out << "---------------" << endl;
< out << endl;
<
<
< Vector<Address> nackedPCKeys = m_nackPCMap_ptr->keys();
< nackedPCKeys.sortVector();
< out << endl;
< out << "------- xact Nacks by PC --------" << endl;
< for(int i=0; i<nackedPCKeys.size(); i++) {
< Address key = nackedPCKeys[i];
< int count = m_nackPCMap_ptr->lookup(key);
< out << "xact_Nack " << key << " "
< << setw(4) << dec << count
< << endl;
< }
< out << "---------------" << endl;
< out << endl;
<
<
< Vector<int> xactExceptionKeys = m_xactExceptionMap_ptr->keys();
< xactExceptionKeys.sortVector();
< out << "------- xact exceptions --------" << endl;
< for(int i=0; i<xactExceptionKeys.size(); i++) {
< int key = xactExceptionKeys[i];
< int count = m_xactExceptionMap_ptr->lookup(key);
< out << "xact_exception("
< << hex << key << "):"
< << setw(4) << dec << count
< << endl;
< }
< out << endl;
< out << "---------------" << endl;
< out << endl;
<
< Vector<int> abortIDKeys = m_abortIDMap_ptr->keys();
< abortIDKeys.sortVector();
< out << "------- xact abort by XID --------" << endl;
< for(int i=0; i<abortIDKeys.size(); i++) {
< int count = m_abortIDMap_ptr->lookup(abortIDKeys[i]);
< out << "xact_aborts("
< << dec << abortIDKeys[i] << "):"
< << setw(7) << count
< << endl;
< }
< out << endl;
< out << "---------------" << endl;
< out << endl;
<
< Vector<Address> abortedPCKeys = m_abortPCMap_ptr->keys();
< abortedPCKeys.sortVector();
< out << endl;
< out << "------- xact Aborts by PC --------" << endl;
< for(int i=0; i<abortedPCKeys.size(); i++) {
< Address key = abortedPCKeys[i];
< int count = m_abortPCMap_ptr->lookup(key);
< out << "xact_abort_pc " << key
< << setw(4) << dec << count
< << endl;
< }
< out << "---------------" << endl;
< out << endl;
<
< Vector<Address> abortedAddrKeys = m_abortAddressMap_ptr->keys();
< abortedAddrKeys.sortVector();
< out << endl;
< out << "------- xact Aborts by Address --------" << endl;
< for(int i=0; i<abortedAddrKeys.size(); i++) {
< Address key = abortedAddrKeys[i];
< int count = m_abortAddressMap_ptr->lookup(key);
< out << "xact_abort_address " << key
< << setw(4) << dec << count
< << endl;
< }
< out << "---------------" << endl;
< out << endl;
< } // !short_stats
<
< Vector<int> commitIDKeys = m_commitIDMap_ptr->keys();
< commitIDKeys.sortVector();
< out << "------- xact Commit Stats by XID --------" << endl;
< for(int i=0; i<commitIDKeys.size(); i++) {
< int count = m_commitIDMap_ptr->lookup(commitIDKeys[i]);
< double retry_count = (double)m_xactRetryIDMap_ptr->lookup(commitIDKeys[i]) / count;
< double cycles_count = (double)m_xactCyclesIDMap_ptr->lookup(commitIDKeys[i]) / count;
< double readset_count = (double)m_xactReadSetIDMap_ptr->lookup(commitIDKeys[i]) / count;
< double writeset_count = (double)m_xactWriteSetIDMap_ptr->lookup(commitIDKeys[i]) / count;
< double loadmiss_count = (double)m_xactLoadMissIDMap_ptr->lookup(commitIDKeys[i]) / count;
< double storemiss_count = (double)m_xactStoreMissIDMap_ptr->lookup(commitIDKeys[i]) / count;
< double instr_count = (double)m_xactInstrCountIDMap_ptr->lookup(commitIDKeys[i]) / count;
< out << "xact_stats id: "
< << dec << commitIDKeys[i]
< << " count: " << setw(7) << count
< << " Cycles: " << setw(7) << cycles_count
< << " Instr: " << setw(7) << instr_count
< << " ReadSet: " << setw(7) << readset_count
< << " WriteSet: " << setw(7) << writeset_count
< << " LoadMiss: " << setw(7) << loadmiss_count
< << " StoreMiss: " << setw(7) << storemiss_count
< << " Retry Count: " << setw(7) << retry_count
< << endl;
< }
< out << endl;
< out << "---------------" << endl;
< out << endl;
<
< if (!short_stats) {
< Vector<int> procsInXactKeys = m_procsInXactMap_ptr->keys();
< procsInXactKeys.sortVector();
< out << "------- xact histogram --------" << endl;
< for(int i=0; i<procsInXactKeys.size(); i++) {
< int count = m_procsInXactMap_ptr->lookup(procsInXactKeys[i]);
< int key = procsInXactKeys[i];
< out << "xact_histogram("
< << dec << key << "):"
< << setw(8) << count
< << endl;
< }
< out << endl;
< out << "---------------" << endl;
< out << endl;
<
< // Read/Write set Bloom filter stats
< //int false_reads = 0;
< long long int false_reads = m_readSetNoMatch;
< Vector<Address> fp_read_keys = m_readSetNoMatch_ptr->keys();
< out << "------- xact read set false positives -------" << endl;
< for(int i=0; i < fp_read_keys.size(); ++i){
< int count = m_readSetNoMatch_ptr->lookup(fp_read_keys[i]);
< //out << "read_false_positive( " << fp_read_keys[i] << " ): "
< // << setw(8) << dec << count << endl;
< false_reads += count;
< }
< out << "Total read set false positives : " << setw(8) << false_reads << endl;
< out << "-----------------------" << endl;
< out << endl;
<
< //int matching_reads = 0;
< long long int matching_reads = m_readSetMatch;
< long long int empty_checks = m_readSetEmptyChecks;
< Vector<Address> read_keys = m_readSetMatch_ptr->keys();
< out << "------- xact read set matches -------" << endl;
< for(int i=0; i < read_keys.size(); ++i){
< int count = m_readSetMatch_ptr->lookup(read_keys[i]);
< //out << "read_match( " << read_keys[i] << " ): "
< // << setw(8) << dec << count << endl;
< matching_reads += count;
< }
< out << "Total read set matches : " << setw(8) << matching_reads << endl;
< out << "Total read set empty checks : " << setw(8) << empty_checks << endl;
< double false_positive_pct = 0.0;
< if((false_reads + matching_reads)> 0){
< false_positive_pct = (1.0*false_reads)/(false_reads+matching_reads)*100.0;
< }
< out << "Read set false positives rate : " << false_positive_pct << "%" << endl;
< out << "-----------------------" << endl;
< out << endl;
<
< // for write set
< //int false_writes = 0;
< long long int false_writes = m_writeSetNoMatch;
< Vector<Address> fp_write_keys = m_writeSetNoMatch_ptr->keys();
< out << "------- xact write set false positives -------" << endl;
< for(int i=0; i < fp_write_keys.size(); ++i){
< int count = m_writeSetNoMatch_ptr->lookup(fp_write_keys[i]);
< //out << "write_false_positive( " << fp_write_keys[i] << " ): "
< // << setw(8) << dec << count << endl;
< false_writes += count;
< }
< out << "Total write set false positives : " << setw(8) << false_writes << endl;
< out << "-----------------------" << endl;
< out << endl;
<
< //int matching_writes = 0;
< long long int matching_writes = m_writeSetMatch;
< empty_checks = m_writeSetEmptyChecks;
< Vector<Address> write_keys = m_writeSetMatch_ptr->keys();
< out << "------- xact write set matches -------" << endl;
< for(int i=0; i < write_keys.size(); ++i){
< int count = m_writeSetMatch_ptr->lookup(write_keys[i]);
< //out << "write_match( " << write_keys[i] << " ): "
< // << setw(8) << dec << count << endl;
< matching_writes += count;
< }
< out << "Total write set matches : " << setw(8) << matching_writes << endl;
< out << "Total write set empty checks : " << setw(8) << empty_checks << endl;
< false_positive_pct = 0.0;
< if((matching_writes+false_writes) > 0){
< false_positive_pct = (1.0*false_writes)/(false_writes+matching_writes)*100.0;
< }
< out << "Write set false positives rate : " << false_positive_pct << "%" << endl;
< out << "-----------------------" << endl;
< out << endl;
<
< out << "----- Xact Signature Stats ------" << endl;
< Vector<int> xids = m_xactReadFilterBitsSetOnCommit->keys();
< for(int i=0; i < xids.size(); ++i){
< int xid = xids[i];
< out << "xid " << xid << " Read set bits set on commit: " << (m_xactReadFilterBitsSetOnCommit->lookup(xid)) << endl;
< }
< xids = m_xactWriteFilterBitsSetOnCommit->keys();
< for(int i=0; i < xids.size(); ++i){
< int xid = xids[i];
< out << "xid " << xid << " Write set bits set on commit: " << (m_xactWriteFilterBitsSetOnCommit->lookup(xid)) << endl;
< }
< xids = m_xactReadFilterBitsSetOnAbort->keys();
< for(int i=0; i < xids.size(); ++i){
< int xid = xids[i];
< out << "xid " << xid << " Read set bits set on abort: " << (m_xactReadFilterBitsSetOnAbort->lookup(xid)) << endl;
< }
< xids = m_xactWriteFilterBitsSetOnAbort->keys();
< for(int i=0; i < xids.size(); ++i){
< int xid = xids[i];
< out << "xid " << xid << " Write set bits set on abort: " << (m_xactWriteFilterBitsSetOnAbort->lookup(xid)) << endl;
< }
< out << endl;
<
< cout << "------- WATCHPOINTS --------" << endl;
< cout << "False Triggers : " << m_watchpointsFalsePositiveTrigger << endl;
< cout << "True Triggers : " << m_watchpointsTrueTrigger << endl;
< cout << "Total Triggers : " << m_watchpointsTrueTrigger + m_watchpointsFalsePositiveTrigger << endl;
< cout << "---------------" << endl;
< cout << endl;
< } // !short_stats
< //m_xact_profiler_ptr->printStats(out, short_stats); // gem5:Arka for decomissioning of log_tm
< } // XACT_MEMORY
<
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< //m_xact_profiler_ptr->clearStats(); //gem5:Arka for decomissiong of log_tm
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< //---- begin XACT_MEM code
< ASSERT(m_xactExceptionMap_ptr != NULL);
< ASSERT(m_procsInXactMap_ptr != NULL);
< ASSERT(m_abortIDMap_ptr != NULL);
< ASSERT(m_abortPCMap_ptr != NULL);
< ASSERT( m_nackXIDMap_ptr != NULL);
< ASSERT(m_nackPCMap_ptr != NULL);
<
< m_abortStarupDelay = -1;
< m_abortPerBlockDelay = -1;
< m_transWBs = 0;
< m_extraWBs = 0;
< m_transactionAborts = 0;
< m_transactionLogOverflows = 0;
< m_transactionCacheOverflows = 0;
< m_transactionUnsupInsts = 0;
< m_transactionSaveRestAborts = 0;
< m_inferredAborts = 0;
< m_xactNacked = 0;
<
< m_xactLogs.clear();
< m_xactCycles.clear();
< m_xactReads.clear();
< m_xactWrites.clear();
< m_xactSizes.clear();
< m_abortDelays.clear();
< m_xactRetries.clear();
< m_xactOverflowReads.clear();
< m_xactOverflowWrites.clear();
< m_xactLoadMisses.clear();
< m_xactStoreMisses.clear();
< m_xactOverflowTotalReads.clear();
< m_xactOverflowTotalWrites.clear();
<
< m_xactExceptionMap_ptr->clear();
< m_procsInXactMap_ptr->clear();
< m_abortIDMap_ptr->clear();
< m_commitIDMap_ptr->clear();
< m_xactRetryIDMap_ptr->clear();
< m_xactCyclesIDMap_ptr->clear();
< m_xactReadSetIDMap_ptr->clear();
< m_xactWriteSetIDMap_ptr->clear();
< m_xactLoadMissIDMap_ptr->clear();
< m_xactStoreMissIDMap_ptr->clear();
< m_xactInstrCountIDMap_ptr->clear();
< m_abortPCMap_ptr->clear();
< m_abortAddressMap_ptr->clear();
< m_nackXIDMap_ptr->clear();
< m_nackXIDPairMap_ptr->clear();
< m_nackPCMap_ptr->clear();
<
< m_xactReadFilterBitsSetOnCommit->clear();
< m_xactReadFilterBitsSetOnAbort->clear();
< m_xactWriteFilterBitsSetOnCommit->clear();
< m_xactWriteFilterBitsSetOnAbort->clear();
<
< m_readSetEmptyChecks = 0;
< m_readSetMatch = 0;
< m_readSetNoMatch = 0;
< m_writeSetEmptyChecks = 0;
< m_writeSetMatch = 0;
< m_writeSetNoMatch = 0;
<
< m_xact_visualizer_last = 0;
< m_watchpointsFalsePositiveTrigger = 0;
< m_watchpointsTrueTrigger = 0;
< //---- end XACT_MEM code
<
1359a952,972
> // For MemoryControl:
> void Profiler::profileMemReq(int bank) {
> m_memReq++;
> m_memBankCount[bank]++;
> }
>
> void Profiler::profileMemBankBusy() { m_memBankBusy++; }
> void Profiler::profileMemBusBusy() { m_memBusBusy++; }
> void Profiler::profileMemReadWriteBusy() { m_memReadWriteBusy++; }
> void Profiler::profileMemDataBusBusy() { m_memDataBusBusy++; }
> void Profiler::profileMemTfawBusy() { m_memTfawBusy++; }
> void Profiler::profileMemRefresh() { m_memRefresh++; }
> void Profiler::profileMemRead() { m_memRead++; }
> void Profiler::profileMemWrite() { m_memWrite++; }
> void Profiler::profileMemWaitCycles(int cycles) { m_memWaitCycles += cycles; }
> void Profiler::profileMemInputQ(int cycles) { m_memInputQ += cycles; }
> void Profiler::profileMemBankQ(int cycles) { m_memBankQ += cycles; }
> void Profiler::profileMemArbWait(int cycles) { m_memArbWait += cycles; }
> void Profiler::profileMemRandBusy() { m_memRandBusy++; }
> void Profiler::profileMemNotOld() { m_memNotOld++; }
>
1413,2294d1025
< //---- begin Transactional Memory CODE
< void Profiler::profileTransaction(int size, int logSize, int readS, int writeS, int overflow_readS, int overflow_writeS, int retries, int useful_cycles, bool nacked, int loadMisses, int storeMisses, int instrCount, int xid){
< m_xactLogs.add(logSize);
< m_xactSizes.add(size);
< m_xactReads.add(readS);
< m_xactWrites.add(writeS);
< m_xactRetries.add(retries);
< m_xactCycles.add(useful_cycles);
< m_xactLoadMisses.add(loadMisses);
< m_xactStoreMisses.add(storeMisses);
< m_xactInstrCount.add(instrCount);
<
< // was this transaction nacked?
< if(nacked){
< m_xactNacked++;
< }
<
< // for overflowed transactions
< if(overflow_readS > 0 || overflow_writeS > 0){
< m_xactOverflowReads.add(overflow_readS);
< m_xactOverflowWrites.add(overflow_writeS);
< m_xactOverflowTotalReads.add(readS);
< m_xactOverflowTotalWrites.add(writeS);
< }
<
< // Record commits by xid
< if(!m_commitIDMap_ptr->exist(xid)){
< m_commitIDMap_ptr->add(xid, 1);
< m_xactRetryIDMap_ptr->add(xid, retries);
< m_xactCyclesIDMap_ptr->add(xid, useful_cycles);
< m_xactReadSetIDMap_ptr->add(xid, readS);
< m_xactWriteSetIDMap_ptr->add(xid, writeS);
< m_xactLoadMissIDMap_ptr->add(xid, loadMisses);
< m_xactStoreMissIDMap_ptr->add(xid, storeMisses);
< m_xactInstrCountIDMap_ptr->add(xid, instrCount);
< } else {
< (m_commitIDMap_ptr->lookup(xid))++;
< (m_xactRetryIDMap_ptr->lookup(xid)) += retries;
< (m_xactCyclesIDMap_ptr->lookup(xid)) += useful_cycles;
< (m_xactReadSetIDMap_ptr->lookup(xid)) += readS;
< (m_xactWriteSetIDMap_ptr->lookup(xid)) += writeS;
< (m_xactLoadMissIDMap_ptr->lookup(xid)) += loadMisses;
< (m_xactStoreMissIDMap_ptr->lookup(xid)) += storeMisses;
< (m_xactInstrCountIDMap_ptr->lookup(xid)) += instrCount;
< }
< }
<
< void Profiler::profileBeginTransaction(NodeID id, int tid, int xid, int thread, Address pc, bool isOpen){
< //- if(PROFILE_XACT){
< if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 2)){
< const char* openStr = isOpen ? " OPEN" : " CLOSED";
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< physical_address_t myPhysPC = SIMICS_translate_address(id, pc);
< integer_t myInst = SIMICS_read_physical_memory(id, myPhysPC, 4);
< const char *myInstStr = SIMICS_disassemble_physical(id, myPhysPC);
< // The actual processor number
< int proc_no = id*RubyConfig::numberofSMTThreads() + thread;
< (* debug_cout_ptr).flags(ios::right);
< (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< (* debug_cout_ptr) << setw(ID_SPACES) << proc_no << " [" << id << "," << thread << "]" << " TID " << tid
< << " XACT BEGIN " << xid
< << " PC 0x" << hex << pc.getAddress()
< << dec
< << " *PC 0x" << hex << myInst << dec
< << " '" << myInstStr << "'"
< << openStr
< << endl;
< }
< }
<
< void Profiler::profileCommitTransaction(NodeID id, int tid, int xid, int thread, Address pc, bool isOpen){
< //- if(PROFILE_XACT){
< if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 2)){
< const char* openStr = isOpen ? " OPEN" : " CLOSED";
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< physical_address_t myPhysPC = SIMICS_translate_address(id, pc);
< integer_t myInst = SIMICS_read_physical_memory(id, myPhysPC, 4);
< const char *myInstStr = SIMICS_disassemble_physical(id, myPhysPC);
< // The actual processor number
< int proc_no = id*RubyConfig::numberofSMTThreads() + thread;
< (* debug_cout_ptr).flags(ios::right);
< (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< (* debug_cout_ptr) << setw(ID_SPACES) << proc_no << " [" << id << "," << thread << "]" << " TID " << tid
< << " XACT COMMIT " << xid
< << " PC 0x" << hex << pc.getAddress()
< << dec
< << " *PC 0x" << hex << myInst << dec
< << " '" << myInstStr << "'"
< << openStr
< << endl;
< }
<
< }
<
< // for profiling overflows
< void Profiler::profileLoadOverflow(NodeID id, int tid, int xid, int thread, Address addr, bool l1_overflow){
< //- if(PROFILE_XACT){
< if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 1)){
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< string overflow_str = " XACT LOAD L1 OVERFLOW ";
< if(!l1_overflow){
< overflow_str = " XACT LOAD L2 OVERFLOW ";
< }
< // The actual processor number
< int proc_no = id*RubyConfig::numberofSMTThreads() + thread;
< (* debug_cout_ptr).flags(ios::right);
< (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< (* debug_cout_ptr) << setw(ID_SPACES) << proc_no << " [" << id << "," << thread << "]" << " TID " << tid
< << overflow_str << xid
< << " ADDR " << addr
< << endl;
< }
< }
<
< // for profiling overflows
< void Profiler::profileStoreOverflow(NodeID id, int tid, int xid, int thread, Address addr, bool l1_overflow){
< //- if(PROFILE_XACT){
< if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 1)){
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< string overflow_str = " XACT STORE L1 OVERFLOW ";
< if(!l1_overflow){
< overflow_str = " XACT STORE L2 OVERFLOW ";
< }
< // The actual processor number
< int proc_no = id*RubyConfig::numberofSMTThreads() + thread;
< (* debug_cout_ptr).flags(ios::right);
< (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< (* debug_cout_ptr) << setw(ID_SPACES) << proc_no << " [" << id << "," << thread << "]" << " TID " << tid
< << overflow_str << xid
< << " ADDR " << addr
< << endl;
< }
< }
<
< void Profiler::profileLoadTransaction(NodeID id, int tid, int xid, int thread, Address addr, Address logicalAddress, Address pc){
< //- if(PROFILE_XACT){
< if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 3)){
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< physical_address_t myPhysPC = SIMICS_translate_address(id, pc);
< integer_t myInst = SIMICS_read_physical_memory(id, myPhysPC, 4);
< const char *myInstStr = SIMICS_disassemble_physical(id, myPhysPC);
< // The actual processor number
< int proc_no = id*RubyConfig::numberofSMTThreads() + thread;
< (* debug_cout_ptr).flags(ios::right);
< (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< (* debug_cout_ptr) << setw(ID_SPACES) << proc_no << " [" << id << "," << thread << "]" << " TID " << tid
< << " XACT LOAD " << xid
< << " " << addr
< << " VA " << logicalAddress
< << " PC " << pc
< << " *PC 0x" << hex << myInst << dec
< << " '" << myInstStr << "'"
< //<< " VAL 0x" << hex << SIMICS_read_physical_memory(proc_no, SIMICS_translate_data_address(proc_no, logicalAddress), 4) << dec
< << " VAL 0x" << hex << g_system_ptr->getDriver()->readPhysicalMemory(proc_no, addr.getAddress(), 4) << dec
< << endl;
< }
< }
<
< void Profiler::profileLoad(NodeID id, int tid, int xid, int thread, Address addr, Address logicalAddress, Address pc){
< if(PROFILE_NONXACT){
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< // The actual processor number
< int proc_no = id*RubyConfig::numberofSMTThreads() + thread;
< (* debug_cout_ptr).flags(ios::right);
< (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< (* debug_cout_ptr) << setw(ID_SPACES) << proc_no << " [" << id << "," << thread << "]" << " TID " << tid
< << " LOAD " << xid
< << " " << addr
< << " VA " << logicalAddress
< << " PC " << pc
< //<< " VAL 0x" << hex << SIMICS_read_physical_memory(proc_no, SIMICS_translate_data_address(proc_no, logicalAddress), 4) << dec
< << " VAL 0x" << hex << g_system_ptr->getDriver()->readPhysicalMemory(proc_no, addr.getAddress(), 4) << dec
< << endl;
< }
< }
<
< void Profiler::profileStoreTransaction(NodeID id, int tid, int xid, int thread, Address addr, Address logicalAddress, Address pc){
< //- if(PROFILE_XACT){
< if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 3)){
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< physical_address_t myPhysPC = SIMICS_translate_address(id, pc);
< integer_t myInst = SIMICS_read_physical_memory(id, myPhysPC, 4);
< const char *myInstStr = SIMICS_disassemble_physical(id, myPhysPC);
< // The actual processor number
< int proc_no = id*RubyConfig::numberofSMTThreads() + thread;
< (* debug_cout_ptr).flags(ios::right);
< (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< (* debug_cout_ptr) << setw(ID_SPACES) << proc_no << " [" << id << "," << thread << "]" << " TID " << tid
< << " XACT STORE " << xid
< << " " << addr
< << " VA " << logicalAddress
< << " PC " << pc
< << " *PC 0x" << hex << myInst << dec
< << " '" << myInstStr << "'"
< << endl;
< }
< }
<
< void Profiler::profileStore(NodeID id, int tid, int xid, int thread, Address addr, Address logicalAddress, Address pc){
< if(PROFILE_NONXACT){
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< // The actual processor number
< int proc_no = id*RubyConfig::numberofSMTThreads() + thread;
< (* debug_cout_ptr).flags(ios::right);
< (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< (* debug_cout_ptr) << setw(ID_SPACES) << proc_no << " [" << id << "," << thread << "]" << " TID " << tid
< << " STORE " << xid
< << " " << addr
< << " VA " << logicalAddress
< << " PC " << pc
< << endl;
< }
< }
<
< void Profiler::profileNack(NodeID id, int tid, int xid, int thread, int nacking_thread, NodeID nackedBy, Address addr, Address logicalAddress, Address pc, uint64 seq_ts, uint64 nack_ts, bool possibleCycle){
< int nid = 0; // g_system_ptr->getChip(nackedBy/RubyConfig::numberOfProcsPerChip())->getTransactionInterfaceManager(nackedBy%RubyConfig::numberOfProcsPerChip())->getXID(nacking_thread);
< assert(0);
< //- if(PROFILE_XACT){
< if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 1)){
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< physical_address_t myPhysPC = SIMICS_translate_address(id, pc);
< integer_t myInst = SIMICS_read_physical_memory(id, myPhysPC, 4);
< const char *myInstStr = SIMICS_disassemble_physical(id, myPhysPC);
< // The actual processor number
< int proc_no = id*g_NUM_SMT_THREADS + thread;
< int nack_proc_no = nackedBy*g_NUM_SMT_THREADS + nacking_thread;
< Address nack_pc = SIMICS_get_program_counter(nack_proc_no);
< (* debug_cout_ptr).flags(ios::right);
< (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< (* debug_cout_ptr) << setw(ID_SPACES) << proc_no << " [" << id << "," << thread << "]" << " TID " << tid
< << " XACT NACK " << xid
< << " by " << nack_proc_no
< << " [ " << nackedBy
< << ", " << nacking_thread
< << " ]"
< << " NID: " << nid
< << " " << addr
< << " VA " << logicalAddress
< << " PC " << pc
< << " *PC 0x" << hex << myInst << dec
< << " '" << myInstStr << "'"
< << " NackerPC " << nack_pc
< << " my_ts " << seq_ts
< << " nack_ts " << nack_ts
< << " possible_cycle " << possibleCycle
< << endl;
< }
<
< // Record nacks by xid
< if(!m_nackXIDMap_ptr->exist(xid)){
< m_nackXIDMap_ptr->add(xid, 1);
< } else {
< (m_nackXIDMap_ptr->lookup(xid))++;
< }
<
< // Record nack ID pairs by xid
< if(!m_nackXIDPairMap_ptr->exist(xid)){
< Map<int, int> * new_map = new Map<int, int>;
< new_map->add(nid, 1);
< m_nackXIDPairMap_ptr->add(xid, new_map);
< }
< else{
< // retrieve existing map
< Map<int, int> * my_map = m_nackXIDPairMap_ptr->lookup(xid);
< if(!my_map->exist(nid)){
< my_map->add(nid, 1);
< }
< else{
< (my_map->lookup(nid))++;
< }
< }
<
< // Record nacks by pc
< if(!m_nackPCMap_ptr->exist(pc)){
< m_nackPCMap_ptr->add(pc, 1);
< } else {
< (m_nackPCMap_ptr->lookup(pc))++;
< }
< }
<
< void Profiler::profileExposedConflict(NodeID id, int xid, int thread, Address addr, Address pc){
< //if(PROFILE_XACT){
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< // The actual processor number
< int proc_no = id*g_NUM_SMT_THREADS + thread;
< (* debug_cout_ptr).flags(ios::right);
< (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< (* debug_cout_ptr) << setw(ID_SPACES) << proc_no << " [" << id << "," << thread << "]" << " "
< << " EXPOSED ACTION CONFLICT " << xid
< << " ADDR " << addr
< << " PC " << pc
< << endl;
< //}
< }
<
< void Profiler::profileInferredAbort(){
< m_inferredAborts++;
< }
<
< void Profiler::profileAbortDelayConstants(int startupDelay, int perBlock){
< m_abortStarupDelay = startupDelay;
< m_abortPerBlockDelay = perBlock;
< }
<
< void Profiler::profileAbortTransaction(NodeID id, int tid, int xid, int thread, int delay, int abortingThread, int abortingProc, Address addr, Address pc){
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< int abortingXID = -1;
< // The actual processor number
< int proc_no = id*g_NUM_SMT_THREADS + thread;
< // we are passed in physical proc number. Compute logical abort proc_no
< int logical_abort_proc_no = abortingProc/g_NUM_SMT_THREADS;
< if(abortingProc >= 0){
< AbstractChip * c = g_system_ptr->getChip(logical_abort_proc_no/RubyConfig::numberOfProcsPerChip());
< abortingXID = 0; // c->getTransactionInterfaceManager(logical_abort_proc_no%RubyConfig::numberOfProcsPerChip())->getXID(abortingThread);
< assert(0);
< }
< //- if(PROFILE_XACT){
< if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 1)){
< physical_address_t myPhysPC = SIMICS_translate_address(id, pc);
< integer_t myInst = SIMICS_read_physical_memory(id, myPhysPC, 4);
< const char *myInstStr = SIMICS_disassemble_physical(id, myPhysPC);
< (* debug_cout_ptr).flags(ios::right);
< (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< (* debug_cout_ptr) << setw(ID_SPACES) << proc_no << " [" << id << "," << thread << "]" << " TID " << tid
< << " XACT ABORT " << xid
< << " caused by " << abortingProc
< << " [ " << logical_abort_proc_no
< << ", " << abortingThread
< << " ]"
< << " xid: " << abortingXID << " "
< << " address: " << addr
< << " delay: " << delay
< << " PC " << pc
< << " *PC 0x" << hex << myInst << dec
< << " '" << myInstStr << "'"
< << endl;
< }
< m_transactionAborts++;
<
< // Record aborts by xid
< if(!m_abortIDMap_ptr->exist(xid)){
< m_abortIDMap_ptr->add(xid, 1);
< } else {
< (m_abortIDMap_ptr->lookup(xid))++;
< }
< m_abortDelays.add(delay);
<
< // Record aborts by pc
< if(!m_abortPCMap_ptr->exist(pc)){
< m_abortPCMap_ptr->add(pc, 1);
< } else {
< (m_abortPCMap_ptr->lookup(pc))++;
< }
<
< // Record aborts by address
< if(!m_abortAddressMap_ptr->exist(addr)){
< m_abortAddressMap_ptr->add(addr, 1);
< } else {
< (m_abortAddressMap_ptr->lookup(addr))++;
< }
< }
<
< void Profiler::profileTransWB(){
< m_transWBs++;
< }
<
< void Profiler::profileExtraWB(){
< m_extraWBs++;
< }
<
< void Profiler::profileXactChange(int procs, int cycles){
< if(!m_procsInXactMap_ptr->exist(procs)){
< m_procsInXactMap_ptr->add(procs, cycles);
< } else {
< (m_procsInXactMap_ptr->lookup(procs)) += cycles;
< }
< }
<
< void Profiler::profileReadSet(Address addr, bool bf_filter_result, bool perfect_filter_result, NodeID id, int thread){
< // do NOT count instances when signature is empty!
< if(!bf_filter_result && !perfect_filter_result){
< m_readSetEmptyChecks++;
< return;
< }
<
< if(bf_filter_result != perfect_filter_result){
< m_readSetNoMatch++;
< /*
< // we have a false positive
< if(!m_readSetNoMatch_ptr->exist(addr)){
< m_readSetNoMatch_ptr->add(addr, 1);
< }
< else{
< (m_readSetNoMatch_ptr->lookup(addr))++;
< }
< */
< }
< else{
< m_readSetMatch++;
< /*
< // Bloom filter agrees with perfect filter
< if(!m_readSetMatch_ptr->exist(addr)){
< m_readSetMatch_ptr->add(addr, 1);
< }
< else{
< (m_readSetMatch_ptr->lookup(addr))++;
< }
< */
< }
< }
<
<
< void Profiler::profileRemoteReadSet(Address addr, bool bf_filter_result, bool perfect_filter_result, NodeID id, int thread){
< if(bf_filter_result != perfect_filter_result){
< // we have a false positive
< if(!m_remoteReadSetNoMatch_ptr->exist(addr)){
< m_remoteReadSetNoMatch_ptr->add(addr, 1);
< }
< else{
< (m_remoteReadSetNoMatch_ptr->lookup(addr))++;
< }
< }
< else{
< // Bloom filter agrees with perfect filter
< if(!m_remoteReadSetMatch_ptr->exist(addr)){
< m_remoteReadSetMatch_ptr->add(addr, 1);
< }
< else{
< (m_remoteReadSetMatch_ptr->lookup(addr))++;
< }
< }
< }
<
< void Profiler::profileWriteSet(Address addr, bool bf_filter_result, bool perfect_filter_result, NodeID id, int thread){
< // do NOT count instances when signature is empty!
< if(!bf_filter_result && !perfect_filter_result){
< m_writeSetEmptyChecks++;
< return;
< }
<
< if(bf_filter_result != perfect_filter_result){
< m_writeSetNoMatch++;
< /*
< // we have a false positive
< if(!m_writeSetNoMatch_ptr->exist(addr)){
< m_writeSetNoMatch_ptr->add(addr, 1);
< }
< else{
< (m_writeSetNoMatch_ptr->lookup(addr))++;
< }
< */
< }
< else{
< m_writeSetMatch++;
< /*
< // Bloom filter agrees with perfect filter
< if(!m_writeSetMatch_ptr->exist(addr)){
< m_writeSetMatch_ptr->add(addr, 1);
< }
< else{
< (m_writeSetMatch_ptr->lookup(addr))++;
< }
< */
< }
< }
<
<
< void Profiler::profileRemoteWriteSet(Address addr, bool bf_filter_result, bool perfect_filter_result, NodeID id, int thread){
< if(bf_filter_result != perfect_filter_result){
< // we have a false positive
< if(!m_remoteWriteSetNoMatch_ptr->exist(addr)){
< m_remoteWriteSetNoMatch_ptr->add(addr, 1);
< }
< else{
< (m_remoteWriteSetNoMatch_ptr->lookup(addr))++;
< }
< }
< else{
< // Bloom filter agrees with perfect filter
< if(!m_remoteWriteSetMatch_ptr->exist(addr)){
< m_remoteWriteSetMatch_ptr->add(addr, 1);
< }
< else{
< (m_remoteWriteSetMatch_ptr->lookup(addr))++;
< }
< }
< }
<
< void Profiler::profileTransactionLogOverflow(NodeID id, Address addr, Address pc){
< if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 1)){
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< physical_address_t myPhysPC = SIMICS_translate_address(id, pc);
< integer_t myInst = SIMICS_read_physical_memory(id, myPhysPC, 4);
< const char *myInstStr = SIMICS_disassemble_physical(id, myPhysPC);
< (* debug_cout_ptr).flags(ios::right);
< (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< (* debug_cout_ptr) << setw(ID_SPACES) << id << " "
< << " XACT LOG OVERFLOW"
< << " ADDR " << addr
< << " PC " << pc
< << " *PC 0x" << hex << myInst << dec
< << " '" << myInstStr << "'"
< << endl;
<
< }
< m_transactionLogOverflows++;
< }
<
< void Profiler::profileTransactionCacheOverflow(NodeID id, Address addr, Address pc){
< if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 1)){
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< physical_address_t myPhysPC = SIMICS_translate_address(id, pc);
< integer_t myInst = SIMICS_read_physical_memory(id, myPhysPC, 4);
< const char *myInstStr = SIMICS_disassemble_physical(id, myPhysPC);
< (* debug_cout_ptr).flags(ios::right);
< (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< (* debug_cout_ptr) << setw(ID_SPACES) << id << " "
< << " XACT CACHE OVERFLOW "
< << " ADDR " << addr
< << " PC " << pc
< << " *PC 0x" << hex << myInst << dec
< << " '" << myInstStr << "'"
< << endl;
<
< }
< m_transactionCacheOverflows++;
< }
<
< void Profiler::profileGetCPS(NodeID id, uint32 cps, Address pc){
< if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 1)){
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< physical_address_t myPhysPC = SIMICS_translate_address(id, pc);
< integer_t myInst = SIMICS_read_physical_memory(id, myPhysPC, 4);
< const char *myInstStr = SIMICS_disassemble_physical(id, myPhysPC);
<
< (* debug_cout_ptr).flags(ios::right);
< (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< (* debug_cout_ptr) << setw(ID_SPACES) << id << " "
< << " XACT GET CPS"
< << " PC " << pc
< << " *PC 0x" << hex << myInst << dec
< << " '" << myInstStr << "'"
< << " CPS 0x" << hex << cps << dec
< << endl;
< }
< }
< //---- end Transactional Memory CODE
<
<
< void Profiler::profileExceptionStart(bool xact, NodeID id, int thread, int val, int trap_level, uinteger_t pc, uinteger_t npc){
< if(xact){
< if(!m_xactExceptionMap_ptr->exist(val)){
< m_xactExceptionMap_ptr->add(val, 1);
< } else {
< (m_xactExceptionMap_ptr->lookup(val))++;
< }
< }
<
< if (!xact && !PROFILE_NONXACT) return;
<
< if(PROFILE_EXCEPTIONS){
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< // The actual processor number
< int proc_no = id*g_NUM_SMT_THREADS + thread;
<
< // get the excepting instruction
< const char * instruction;
< physical_address_t addr = SIMICS_translate_address( proc_no, Address(pc));
< if(val != 0x64 && addr != 0x0){
< // ignore instruction TLB miss
< instruction = SIMICS_disassemble_physical( proc_no, addr );
< }
<
< (* debug_cout_ptr).flags(ios::right);
< (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< (* debug_cout_ptr) << setw(ID_SPACES) << proc_no << " [" << id << "," << thread << " ]" << " ";
< if (xact)
< (* debug_cout_ptr) << " XACT Exception(";
< else
< (* debug_cout_ptr) << " Exception(";
<
< (* debug_cout_ptr) << hex << val << dec << ")_START--Trap Level " << trap_level
< << "--(PC=0x" << hex << pc << ", " << npc << ")"
< << dec;
<
< if(val != 0x64 && addr != 0x0){
< (* debug_cout_ptr) << " instruction = " << instruction;
< }
< else{
< (* debug_cout_ptr) << " instruction = INSTRUCTION TLB MISS";
< }
< (* debug_cout_ptr) << dec << endl;
< }
< }
<
< void Profiler::profileExceptionDone(bool xact, NodeID id, int thread, int val, int trap_level, uinteger_t pc, uinteger_t npc, uinteger_t tpc, uinteger_t tnpc){
< if (!xact && !PROFILE_NONXACT) return;
<
< if (PROFILE_EXCEPTIONS){
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< // The actual processor number
< int proc_no = id*g_NUM_SMT_THREADS + thread;
<
< // get the excepting instruction
< const char * instruction;
< instruction = SIMICS_disassemble_physical( proc_no, SIMICS_translate_address( proc_no, Address(pc) ) );
<
<
< (* debug_cout_ptr).flags(ios::right);
< (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< (* debug_cout_ptr) << setw(ID_SPACES) << proc_no << " [" << id << "," << thread << " ]" << " ";
< if (xact)
< (* debug_cout_ptr) << " XACT Exception(";
< else
< (* debug_cout_ptr) << " Exception(";
<
< (* debug_cout_ptr) << hex << val << dec << ")_DONE--Trap Level " << trap_level
< << "--(PC=0x" << hex << pc << ", " << npc << dec << ")"
< << "--(TPC=0x" << hex << tpc << ", " << tnpc << dec << ")"
< << endl;
< }
< }
<
< void Profiler::rubyWatch(int id){
< int rn_g1 = SIMICS_get_register_number(id, "g1");
< uint64 tr = SIMICS_read_register(id, rn_g1);
< Address watch_address = Address(tr);
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
<
< (* debug_cout_ptr).flags(ios::right);
< (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< (* debug_cout_ptr) << setw(ID_SPACES) << id << " "
< << "RUBY WATCH "
< << watch_address
< << endl;
<
< if(!m_watch_address_list_ptr->exist(watch_address)){
< m_watch_address_list_ptr->add(watch_address, 1);
< }
< }
<
< bool Profiler::watchAddress(Address addr){
< if (m_watch_address_list_ptr->exist(addr))
< return true;
< else
< return false;
< }
<
< void Profiler::profileReadFilterBitsSet(int xid, int bits, bool isCommit) {
< if (isCommit) {
< if(!m_xactReadFilterBitsSetOnCommit->exist(xid)){
< Histogram hist;
< hist.add(bits);
< m_xactReadFilterBitsSetOnCommit->add(xid, hist);
< }
< else{
< (m_xactReadFilterBitsSetOnCommit->lookup(xid)).add(bits);
< }
< } else {
< if(!m_xactReadFilterBitsSetOnAbort->exist(xid)){
< Histogram hist;
< hist.add(bits);
< m_xactReadFilterBitsSetOnAbort->add(xid, hist);
< }
< else{
< (m_xactReadFilterBitsSetOnAbort->lookup(xid)).add(bits);
< }
< }
< }
<
< void Profiler::profileWriteFilterBitsSet(int xid, int bits, bool isCommit) {
< if (isCommit) {
< if(!m_xactWriteFilterBitsSetOnCommit->exist(xid)){
< Histogram hist;
< hist.add(bits);
< m_xactWriteFilterBitsSetOnCommit->add(xid, hist);
< }
< else{
< (m_xactWriteFilterBitsSetOnCommit->lookup(xid)).add(bits);
< }
< } else {
< if(!m_xactWriteFilterBitsSetOnAbort->exist(xid)){
< Histogram hist;
< hist.add(bits);
< m_xactWriteFilterBitsSetOnAbort->add(xid, hist);
< }
< else{
< (m_xactWriteFilterBitsSetOnAbort->lookup(xid)).add(bits);
< }
< }
< }
< /*
< //gem5:Arka for decomissioning log_tm
<
< void Profiler::setXactVisualizerFile(char * filename){
< if ( (filename == NULL) ||
< (!strcmp(filename, "none")) ) {
< m_xact_visualizer_ptr = &cout;
< return;
< }
<
< if (m_xact_visualizer.is_open() ) {
< m_xact_visualizer.close ();
< }
< m_xact_visualizer.open (filename, std::ios::out);
< if (! m_xact_visualizer.is_open() ) {
< cerr << "setXactVisualizer: can't open file " << filename << endl;
< }
< else {
< m_xact_visualizer_ptr = &m_xact_visualizer;
< }
< cout << "setXactVisualizer file " << filename << endl;
< }
<
< void Profiler::printTransactionState(bool can_skip){
< if (!XACT_VISUALIZER) return;
< int num_processors = RubyConfig::numberOfProcessors() * RubyConfig::numberofSMTThreads();
<
< if (!g_system_ptr->getXactVisualizer()->existXactActivity() && can_skip)
< return;
<
< if (can_skip && ((g_eventQueue_ptr->getTime()/10000) <= m_xact_visualizer_last))
< return;
<
< Vector<char> xactStateVector = g_system_ptr->getXactVisualizer()->getTransactionStateVector();
< for (int i = 0 ; i < num_processors; i++){
< (* m_xact_visualizer_ptr) << xactStateVector[i] << " ";
< }
< (* m_xact_visualizer_ptr) << " " << g_eventQueue_ptr->getTime() << endl;
< m_xact_visualizer_last = g_eventQueue_ptr->getTime() / 10000;
< }
< */
< void Profiler::watchpointsFalsePositiveTrigger()
< {
< m_watchpointsFalsePositiveTrigger++;
< }
<
< void Profiler::watchpointsTrueTrigger()
< {
< m_watchpointsTrueTrigger++;
< }
<
< // For MemoryControl:
< void Profiler::profileMemReq(int bank) {
< m_memReq++;
< m_memBankCount[bank]++;
< }
< void Profiler::profileMemBankBusy() { m_memBankBusy++; }
< void Profiler::profileMemBusBusy() { m_memBusBusy++; }
< void Profiler::profileMemReadWriteBusy() { m_memReadWriteBusy++; }
< void Profiler::profileMemDataBusBusy() { m_memDataBusBusy++; }
< void Profiler::profileMemTfawBusy() { m_memTfawBusy++; }
< void Profiler::profileMemRefresh() { m_memRefresh++; }
< void Profiler::profileMemRead() { m_memRead++; }
< void Profiler::profileMemWrite() { m_memWrite++; }
< void Profiler::profileMemWaitCycles(int cycles) { m_memWaitCycles += cycles; }
< void Profiler::profileMemInputQ(int cycles) { m_memInputQ += cycles; }
< void Profiler::profileMemBankQ(int cycles) { m_memBankQ += cycles; }
< void Profiler::profileMemArbWait(int cycles) { m_memArbWait += cycles; }
< void Profiler::profileMemRandBusy() { m_memRandBusy++; }
< void Profiler::profileMemNotOld() { m_memNotOld++; }
<
<
< //----------- ATMTP -------------------//
<
< void Profiler::profileTransactionTCC(NodeID id, Address pc){
< if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 1)){
< physical_address_t myPhysPC = SIMICS_translate_address(id, pc);
< integer_t myInst = SIMICS_read_physical_memory(id, myPhysPC, 4);
< const char *myInstStr = SIMICS_disassemble_physical(id, myPhysPC);
<
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< cout.flags(ios::right);
< cout << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< cout << setw(ID_SPACES) << id << " "
< << " XACT Aborting! Executed TCC "
< << " PC: " << pc
< << " *PC: 0x" << hex << myInst << dec
< << " '" << myInstStr << "'"
< << endl;
< }
< m_transactionUnsupInsts++;
< }
<
< void Profiler::profileTransactionUnsupInst(NodeID id, Address pc){
< if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 1)){
< physical_address_t myPhysPC = SIMICS_translate_address(id, pc);
< integer_t myInst = SIMICS_read_physical_memory(id, myPhysPC, 4);
< const char *myInstStr = SIMICS_disassemble_physical(id, myPhysPC);
<
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< cout.flags(ios::right);
< cout << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< cout << setw(ID_SPACES) << id << " "
< << " XACT Aborting! Executed Unsupported Instruction "
< << " PC: " << pc
< << " *PC: 0x" << hex << myInst << dec
< << " '" << myInstStr << "'"
< << endl;
< }
< m_transactionUnsupInsts++;
< }
<
< void Profiler::profileTransactionSaveInst(NodeID id, Address pc){
< if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 1)){
< physical_address_t myPhysPC = SIMICS_translate_address(id, pc);
< integer_t myInst = SIMICS_read_physical_memory(id, myPhysPC, 4);
< const char *myInstStr = SIMICS_disassemble_physical(id, myPhysPC);
<
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< cout.flags(ios::right);
< cout << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< cout << setw(ID_SPACES) << id << " "
< << " XACT Aborting! Executed Save Instruction "
< << " PC: " << pc
< << " *PC: 0x" << hex << myInst << dec
< << " '" << myInstStr << "'"
< << endl;
< }
< m_transactionSaveRestAborts++;
< }
<
< void Profiler::profileTransactionRestoreInst(NodeID id, Address pc){
< if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 1)){
< physical_address_t myPhysPC = SIMICS_translate_address(id, pc);
< integer_t myInst = SIMICS_read_physical_memory(id, myPhysPC, 4);
< const char *myInstStr = SIMICS_disassemble_physical(id, myPhysPC);
<
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< cout.flags(ios::right);
< cout << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< cout << setw(ID_SPACES) << id << " "
< << " XACT Aborting! Executed Restore Instruction "
< << " PC: " << pc
< << " *PC: 0x" << hex << myInst << dec
< << " '" << myInstStr << "'"
< << endl;
< }
< m_transactionSaveRestAborts++;
< }
<
< void Profiler::profileTimerInterrupt(NodeID id,
< uinteger_t tick, uinteger_t tick_cmpr,
< uinteger_t stick, uinteger_t stick_cmpr,
< int trap_level,
< uinteger_t pc, uinteger_t npc,
< uinteger_t pstate, int pil){
< if (PROFILE_EXCEPTIONS) {
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< cout.flags(ios::right);
< cout << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< cout << setw(ID_SPACES) << id << " ";
< cout << hex << "Timer--(Tick=0x" << tick << ", TckCmp=0x" << tick_cmpr
< << ", STick=0x" << stick << ", STickCmp=0x" << stick_cmpr
< << ")--(PC=" << pc << ", " << npc
< << dec << ")--(TL=" << trap_level << ", pil=" << pil
< << hex << ", pstate=0x" << pstate
< << dec << ")" << endl;
< }
< }
< // #include "TransactionInterfaceManager.hh"
< #include "interface.hh"
< //#include "XactVisualizer.hh" //gem5:Arka for decomissioning log_tm
< //#include "XactProfiler.hh" //gem5:Arka for decomissioning log_tm
72,75d67
< // extern "C" {
< // #include "Rock.hh"
< // }
<
80d71
< extern std::ostream * xact_cout_ptr;
100,101d90
< //m_xact_profiler_ptr = new XactProfiler; //gem5:Arka for decomissioning og log_tm
<
107d95
< m_xact_visualizer_ptr = &cout;
109,136d96
< //---- begin XACT_MEM code
< m_xactExceptionMap_ptr = new Map<int, int>;
< m_procsInXactMap_ptr = new Map<int, int>;
< m_abortIDMap_ptr = new Map<int, int>;
< m_commitIDMap_ptr = new Map<int, int>;
< m_xactRetryIDMap_ptr = new Map<int, int>;
< m_xactCyclesIDMap_ptr = new Map<int, int>;
< m_xactReadSetIDMap_ptr = new Map<int, int>;
< m_xactWriteSetIDMap_ptr = new Map<int, int>;
< m_xactLoadMissIDMap_ptr = new Map<int, int>;
< m_xactStoreMissIDMap_ptr = new Map<int, int>;
< m_xactInstrCountIDMap_ptr = new Map<int, integer_t>;
< m_abortPCMap_ptr = new Map<Address, int>;
< m_abortAddressMap_ptr = new Map<Address, int>;
< m_nackXIDMap_ptr = new Map<int, int>;
< m_nackXIDPairMap_ptr = new Map<int, Map<int, int> * >;
< m_nackPCMap_ptr = new Map<Address, int>;
< m_watch_address_list_ptr = new Map<Address, int>;
< m_readSetMatch_ptr = new Map<Address, int>;
< m_readSetNoMatch_ptr = new Map<Address, int>;
< m_writeSetMatch_ptr = new Map<Address, int>;
< m_writeSetNoMatch_ptr = new Map<Address, int>;
< m_xactReadFilterBitsSetOnCommit = new Map<int, Histogram>;
< m_xactReadFilterBitsSetOnAbort = new Map<int, Histogram>;
< m_xactWriteFilterBitsSetOnCommit = new Map<int, Histogram>;
< m_xactWriteFilterBitsSetOnAbort = new Map<int, Histogram>;
< //---- end XACT_MEM code
<
172d131
< //delete m_xact_profiler_ptr; //gem5:Arka for decomissioning of log_tm
195c154
< integer_t simics_cycles_executed = perProcCycleCount.sum();
---
> integer_t cycles_executed = perProcCycleCount.sum();
202c161
< (*m_periodic_output_file_ptr) << "simics_cycles_executed: " << simics_cycles_executed << " " << perProcCycleCount << endl;
---
> (*m_periodic_output_file_ptr) << "cycles_executed: " << cycles_executed << " " << perProcCycleCount << endl;
353c312
< integer_t simics_cycles_executed = perProcCycleCount.sum();
---
> integer_t cycles_executed = perProcCycleCount.sum();
367c326
< out << "simics_cycles_executed: " << simics_cycles_executed << " " << perProcCycleCount << endl;
---
> out << "cycles_executed: " << cycles_executed << " " << perProcCycleCount << endl;
523,820d481
< if (XACT_MEMORY){
< // Transactional Memory stats
< out << "Transactional Memory Stats:" << endl;
< out << "------- xact --------" << endl;
< out << "xact_size_dist: " << m_xactSizes << endl;
< out << "xact_instr_count: " << m_xactInstrCount << endl;
< out << "xact_time_dist: " << m_xactCycles << endl;
< out << "xact_log_size_dist: " << m_xactLogs << endl;
< out << "xact_read_set_size_dist: " << m_xactReads << endl;
< out << "xact_write_set_size_dist: " << m_xactWrites << endl;
< out << "xact_overflow_read_lines_dist: " << m_xactOverflowReads << endl;
< out << "xact_overflow_write_lines_dist: " << m_xactOverflowWrites << endl;
< out << "xact_overflow_read_set_size_dist: " << m_xactOverflowTotalReads << endl;
< out << "xact_overflow_write_set_size_dist: " << m_xactOverflowTotalWrites << endl;
< out << "xact_miss_load_dist: " << m_xactLoadMisses << endl;
< out << "xact_miss_store_dist: " << m_xactStoreMisses << endl;
< out << "xact_nacked: " << m_xactNacked << endl;
< out << "xact_retries: " << m_xactRetries << endl;
< out << "xact_abort_delays: " << m_abortDelays << endl;
< out << "xact_aborts: " << m_transactionAborts << endl;
< if (ATMTP_ENABLED) {
< out << "xact_log_overflows: " << m_transactionLogOverflows << endl;
< out << "xact_cache_overflows: " << m_transactionCacheOverflows << endl;
< out << "xact_unsup_inst_aborts: " << m_transactionUnsupInsts << endl;
< out << "xact_save_rest_aborts: " << m_transactionSaveRestAborts << endl;
< }
< out << "xact_writebacks: " << m_transWBs << endl;
< out << "xact_extra_wbs: " << m_extraWBs << endl;
< out << "xact_handler_startup_delay: " << m_abortStarupDelay << endl;
< out << "xact_handler_per_block_delay: " << m_abortPerBlockDelay << endl;
< out << "xact_inferred_aborts: " << m_inferredAborts << endl;
< //out << "xact_histogram: " << m_procsInXact << endl;
<
< if (!short_stats) {
< Vector<int> nackedXIDKeys = m_nackXIDMap_ptr->keys();
< nackedXIDKeys.sortVector();
< out << endl;
< int total_nacks = 0;
< out << "------- xact Nacks by XID --------" << endl;
< for(int i=0; i<nackedXIDKeys.size(); i++) {
< int key = nackedXIDKeys[i];
< int count = m_nackXIDMap_ptr->lookup(key);
< total_nacks += count;
< out << "xact " << key << " "
< << setw(6) << dec << count
< << endl;
< }
< out << "Total Nacks: " << total_nacks << endl;
< out << "---------------" << endl;
< out << endl;
<
< // Print XID Nack Pairs
< Vector<int> nackedXIDPairKeys = m_nackXIDPairMap_ptr->keys();
< nackedXIDPairKeys.sortVector();
< out << endl;
< total_nacks = 0;
< out << "------- xact Nacks by XID Pairs --------" << endl;
< for(int i=0; i<nackedXIDPairKeys.size(); i++) {
< int key = nackedXIDPairKeys[i];
< Map<int, int> * my_map = m_nackXIDPairMap_ptr->lookup(key);
< Vector<int> my_keys = my_map->keys();
< my_keys.sortVector();
< for(int j=0; j<my_keys.size(); j++){
< int nid = my_keys[j];
< int count = my_map->lookup(nid);
< total_nacks += count;
< out << "xact " << key << " nacked by xact " << nid << " "
< << setw(6) << dec << count
< << endl;
< }
< }
< out << "Total Nacks: " << total_nacks << endl;
< out << "---------------" << endl;
< out << endl;
<
<
< Vector<Address> nackedPCKeys = m_nackPCMap_ptr->keys();
< nackedPCKeys.sortVector();
< out << endl;
< out << "------- xact Nacks by PC --------" << endl;
< for(int i=0; i<nackedPCKeys.size(); i++) {
< Address key = nackedPCKeys[i];
< int count = m_nackPCMap_ptr->lookup(key);
< out << "xact_Nack " << key << " "
< << setw(4) << dec << count
< << endl;
< }
< out << "---------------" << endl;
< out << endl;
<
<
< Vector<int> xactExceptionKeys = m_xactExceptionMap_ptr->keys();
< xactExceptionKeys.sortVector();
< out << "------- xact exceptions --------" << endl;
< for(int i=0; i<xactExceptionKeys.size(); i++) {
< int key = xactExceptionKeys[i];
< int count = m_xactExceptionMap_ptr->lookup(key);
< out << "xact_exception("
< << hex << key << "):"
< << setw(4) << dec << count
< << endl;
< }
< out << endl;
< out << "---------------" << endl;
< out << endl;
<
< Vector<int> abortIDKeys = m_abortIDMap_ptr->keys();
< abortIDKeys.sortVector();
< out << "------- xact abort by XID --------" << endl;
< for(int i=0; i<abortIDKeys.size(); i++) {
< int count = m_abortIDMap_ptr->lookup(abortIDKeys[i]);
< out << "xact_aborts("
< << dec << abortIDKeys[i] << "):"
< << setw(7) << count
< << endl;
< }
< out << endl;
< out << "---------------" << endl;
< out << endl;
<
< Vector<Address> abortedPCKeys = m_abortPCMap_ptr->keys();
< abortedPCKeys.sortVector();
< out << endl;
< out << "------- xact Aborts by PC --------" << endl;
< for(int i=0; i<abortedPCKeys.size(); i++) {
< Address key = abortedPCKeys[i];
< int count = m_abortPCMap_ptr->lookup(key);
< out << "xact_abort_pc " << key
< << setw(4) << dec << count
< << endl;
< }
< out << "---------------" << endl;
< out << endl;
<
< Vector<Address> abortedAddrKeys = m_abortAddressMap_ptr->keys();
< abortedAddrKeys.sortVector();
< out << endl;
< out << "------- xact Aborts by Address --------" << endl;
< for(int i=0; i<abortedAddrKeys.size(); i++) {
< Address key = abortedAddrKeys[i];
< int count = m_abortAddressMap_ptr->lookup(key);
< out << "xact_abort_address " << key
< << setw(4) << dec << count
< << endl;
< }
< out << "---------------" << endl;
< out << endl;
< } // !short_stats
<
< Vector<int> commitIDKeys = m_commitIDMap_ptr->keys();
< commitIDKeys.sortVector();
< out << "------- xact Commit Stats by XID --------" << endl;
< for(int i=0; i<commitIDKeys.size(); i++) {
< int count = m_commitIDMap_ptr->lookup(commitIDKeys[i]);
< double retry_count = (double)m_xactRetryIDMap_ptr->lookup(commitIDKeys[i]) / count;
< double cycles_count = (double)m_xactCyclesIDMap_ptr->lookup(commitIDKeys[i]) / count;
< double readset_count = (double)m_xactReadSetIDMap_ptr->lookup(commitIDKeys[i]) / count;
< double writeset_count = (double)m_xactWriteSetIDMap_ptr->lookup(commitIDKeys[i]) / count;
< double loadmiss_count = (double)m_xactLoadMissIDMap_ptr->lookup(commitIDKeys[i]) / count;
< double storemiss_count = (double)m_xactStoreMissIDMap_ptr->lookup(commitIDKeys[i]) / count;
< double instr_count = (double)m_xactInstrCountIDMap_ptr->lookup(commitIDKeys[i]) / count;
< out << "xact_stats id: "
< << dec << commitIDKeys[i]
< << " count: " << setw(7) << count
< << " Cycles: " << setw(7) << cycles_count
< << " Instr: " << setw(7) << instr_count
< << " ReadSet: " << setw(7) << readset_count
< << " WriteSet: " << setw(7) << writeset_count
< << " LoadMiss: " << setw(7) << loadmiss_count
< << " StoreMiss: " << setw(7) << storemiss_count
< << " Retry Count: " << setw(7) << retry_count
< << endl;
< }
< out << endl;
< out << "---------------" << endl;
< out << endl;
<
< if (!short_stats) {
< Vector<int> procsInXactKeys = m_procsInXactMap_ptr->keys();
< procsInXactKeys.sortVector();
< out << "------- xact histogram --------" << endl;
< for(int i=0; i<procsInXactKeys.size(); i++) {
< int count = m_procsInXactMap_ptr->lookup(procsInXactKeys[i]);
< int key = procsInXactKeys[i];
< out << "xact_histogram("
< << dec << key << "):"
< << setw(8) << count
< << endl;
< }
< out << endl;
< out << "---------------" << endl;
< out << endl;
<
< // Read/Write set Bloom filter stats
< //int false_reads = 0;
< long long int false_reads = m_readSetNoMatch;
< Vector<Address> fp_read_keys = m_readSetNoMatch_ptr->keys();
< out << "------- xact read set false positives -------" << endl;
< for(int i=0; i < fp_read_keys.size(); ++i){
< int count = m_readSetNoMatch_ptr->lookup(fp_read_keys[i]);
< //out << "read_false_positive( " << fp_read_keys[i] << " ): "
< // << setw(8) << dec << count << endl;
< false_reads += count;
< }
< out << "Total read set false positives : " << setw(8) << false_reads << endl;
< out << "-----------------------" << endl;
< out << endl;
<
< //int matching_reads = 0;
< long long int matching_reads = m_readSetMatch;
< long long int empty_checks = m_readSetEmptyChecks;
< Vector<Address> read_keys = m_readSetMatch_ptr->keys();
< out << "------- xact read set matches -------" << endl;
< for(int i=0; i < read_keys.size(); ++i){
< int count = m_readSetMatch_ptr->lookup(read_keys[i]);
< //out << "read_match( " << read_keys[i] << " ): "
< // << setw(8) << dec << count << endl;
< matching_reads += count;
< }
< out << "Total read set matches : " << setw(8) << matching_reads << endl;
< out << "Total read set empty checks : " << setw(8) << empty_checks << endl;
< double false_positive_pct = 0.0;
< if((false_reads + matching_reads)> 0){
< false_positive_pct = (1.0*false_reads)/(false_reads+matching_reads)*100.0;
< }
< out << "Read set false positives rate : " << false_positive_pct << "%" << endl;
< out << "-----------------------" << endl;
< out << endl;
<
< // for write set
< //int false_writes = 0;
< long long int false_writes = m_writeSetNoMatch;
< Vector<Address> fp_write_keys = m_writeSetNoMatch_ptr->keys();
< out << "------- xact write set false positives -------" << endl;
< for(int i=0; i < fp_write_keys.size(); ++i){
< int count = m_writeSetNoMatch_ptr->lookup(fp_write_keys[i]);
< //out << "write_false_positive( " << fp_write_keys[i] << " ): "
< // << setw(8) << dec << count << endl;
< false_writes += count;
< }
< out << "Total write set false positives : " << setw(8) << false_writes << endl;
< out << "-----------------------" << endl;
< out << endl;
<
< //int matching_writes = 0;
< long long int matching_writes = m_writeSetMatch;
< empty_checks = m_writeSetEmptyChecks;
< Vector<Address> write_keys = m_writeSetMatch_ptr->keys();
< out << "------- xact write set matches -------" << endl;
< for(int i=0; i < write_keys.size(); ++i){
< int count = m_writeSetMatch_ptr->lookup(write_keys[i]);
< //out << "write_match( " << write_keys[i] << " ): "
< // << setw(8) << dec << count << endl;
< matching_writes += count;
< }
< out << "Total write set matches : " << setw(8) << matching_writes << endl;
< out << "Total write set empty checks : " << setw(8) << empty_checks << endl;
< false_positive_pct = 0.0;
< if((matching_writes+false_writes) > 0){
< false_positive_pct = (1.0*false_writes)/(false_writes+matching_writes)*100.0;
< }
< out << "Write set false positives rate : " << false_positive_pct << "%" << endl;
< out << "-----------------------" << endl;
< out << endl;
<
< out << "----- Xact Signature Stats ------" << endl;
< Vector<int> xids = m_xactReadFilterBitsSetOnCommit->keys();
< for(int i=0; i < xids.size(); ++i){
< int xid = xids[i];
< out << "xid " << xid << " Read set bits set on commit: " << (m_xactReadFilterBitsSetOnCommit->lookup(xid)) << endl;
< }
< xids = m_xactWriteFilterBitsSetOnCommit->keys();
< for(int i=0; i < xids.size(); ++i){
< int xid = xids[i];
< out << "xid " << xid << " Write set bits set on commit: " << (m_xactWriteFilterBitsSetOnCommit->lookup(xid)) << endl;
< }
< xids = m_xactReadFilterBitsSetOnAbort->keys();
< for(int i=0; i < xids.size(); ++i){
< int xid = xids[i];
< out << "xid " << xid << " Read set bits set on abort: " << (m_xactReadFilterBitsSetOnAbort->lookup(xid)) << endl;
< }
< xids = m_xactWriteFilterBitsSetOnAbort->keys();
< for(int i=0; i < xids.size(); ++i){
< int xid = xids[i];
< out << "xid " << xid << " Write set bits set on abort: " << (m_xactWriteFilterBitsSetOnAbort->lookup(xid)) << endl;
< }
< out << endl;
<
< cout << "------- WATCHPOINTS --------" << endl;
< cout << "False Triggers : " << m_watchpointsFalsePositiveTrigger << endl;
< cout << "True Triggers : " << m_watchpointsTrueTrigger << endl;
< cout << "Total Triggers : " << m_watchpointsTrueTrigger + m_watchpointsFalsePositiveTrigger << endl;
< cout << "---------------" << endl;
< cout << endl;
< } // !short_stats
< //m_xact_profiler_ptr->printStats(out, short_stats); // gem5:Arka for decomissioning of log_tm
< } // XACT_MEMORY
<
996d656
< //m_xact_profiler_ptr->clearStats(); //gem5:Arka for decomissiong of log_tm
998,1065d657
< //---- begin XACT_MEM code
< ASSERT(m_xactExceptionMap_ptr != NULL);
< ASSERT(m_procsInXactMap_ptr != NULL);
< ASSERT(m_abortIDMap_ptr != NULL);
< ASSERT(m_abortPCMap_ptr != NULL);
< ASSERT( m_nackXIDMap_ptr != NULL);
< ASSERT(m_nackPCMap_ptr != NULL);
<
< m_abortStarupDelay = -1;
< m_abortPerBlockDelay = -1;
< m_transWBs = 0;
< m_extraWBs = 0;
< m_transactionAborts = 0;
< m_transactionLogOverflows = 0;
< m_transactionCacheOverflows = 0;
< m_transactionUnsupInsts = 0;
< m_transactionSaveRestAborts = 0;
< m_inferredAborts = 0;
< m_xactNacked = 0;
<
< m_xactLogs.clear();
< m_xactCycles.clear();
< m_xactReads.clear();
< m_xactWrites.clear();
< m_xactSizes.clear();
< m_abortDelays.clear();
< m_xactRetries.clear();
< m_xactOverflowReads.clear();
< m_xactOverflowWrites.clear();
< m_xactLoadMisses.clear();
< m_xactStoreMisses.clear();
< m_xactOverflowTotalReads.clear();
< m_xactOverflowTotalWrites.clear();
<
< m_xactExceptionMap_ptr->clear();
< m_procsInXactMap_ptr->clear();
< m_abortIDMap_ptr->clear();
< m_commitIDMap_ptr->clear();
< m_xactRetryIDMap_ptr->clear();
< m_xactCyclesIDMap_ptr->clear();
< m_xactReadSetIDMap_ptr->clear();
< m_xactWriteSetIDMap_ptr->clear();
< m_xactLoadMissIDMap_ptr->clear();
< m_xactStoreMissIDMap_ptr->clear();
< m_xactInstrCountIDMap_ptr->clear();
< m_abortPCMap_ptr->clear();
< m_abortAddressMap_ptr->clear();
< m_nackXIDMap_ptr->clear();
< m_nackXIDPairMap_ptr->clear();
< m_nackPCMap_ptr->clear();
<
< m_xactReadFilterBitsSetOnCommit->clear();
< m_xactReadFilterBitsSetOnAbort->clear();
< m_xactWriteFilterBitsSetOnCommit->clear();
< m_xactWriteFilterBitsSetOnAbort->clear();
<
< m_readSetEmptyChecks = 0;
< m_readSetMatch = 0;
< m_readSetNoMatch = 0;
< m_writeSetEmptyChecks = 0;
< m_writeSetMatch = 0;
< m_writeSetNoMatch = 0;
<
< m_xact_visualizer_last = 0;
< m_watchpointsFalsePositiveTrigger = 0;
< m_watchpointsTrueTrigger = 0;
< //---- end XACT_MEM code
<
1359a952,972
> // For MemoryControl:
> void Profiler::profileMemReq(int bank) {
> m_memReq++;
> m_memBankCount[bank]++;
> }
>
> void Profiler::profileMemBankBusy() { m_memBankBusy++; }
> void Profiler::profileMemBusBusy() { m_memBusBusy++; }
> void Profiler::profileMemReadWriteBusy() { m_memReadWriteBusy++; }
> void Profiler::profileMemDataBusBusy() { m_memDataBusBusy++; }
> void Profiler::profileMemTfawBusy() { m_memTfawBusy++; }
> void Profiler::profileMemRefresh() { m_memRefresh++; }
> void Profiler::profileMemRead() { m_memRead++; }
> void Profiler::profileMemWrite() { m_memWrite++; }
> void Profiler::profileMemWaitCycles(int cycles) { m_memWaitCycles += cycles; }
> void Profiler::profileMemInputQ(int cycles) { m_memInputQ += cycles; }
> void Profiler::profileMemBankQ(int cycles) { m_memBankQ += cycles; }
> void Profiler::profileMemArbWait(int cycles) { m_memArbWait += cycles; }
> void Profiler::profileMemRandBusy() { m_memRandBusy++; }
> void Profiler::profileMemNotOld() { m_memNotOld++; }
>
1413,2294d1025
< //---- begin Transactional Memory CODE
< void Profiler::profileTransaction(int size, int logSize, int readS, int writeS, int overflow_readS, int overflow_writeS, int retries, int useful_cycles, bool nacked, int loadMisses, int storeMisses, int instrCount, int xid){
< m_xactLogs.add(logSize);
< m_xactSizes.add(size);
< m_xactReads.add(readS);
< m_xactWrites.add(writeS);
< m_xactRetries.add(retries);
< m_xactCycles.add(useful_cycles);
< m_xactLoadMisses.add(loadMisses);
< m_xactStoreMisses.add(storeMisses);
< m_xactInstrCount.add(instrCount);
<
< // was this transaction nacked?
< if(nacked){
< m_xactNacked++;
< }
<
< // for overflowed transactions
< if(overflow_readS > 0 || overflow_writeS > 0){
< m_xactOverflowReads.add(overflow_readS);
< m_xactOverflowWrites.add(overflow_writeS);
< m_xactOverflowTotalReads.add(readS);
< m_xactOverflowTotalWrites.add(writeS);
< }
<
< // Record commits by xid
< if(!m_commitIDMap_ptr->exist(xid)){
< m_commitIDMap_ptr->add(xid, 1);
< m_xactRetryIDMap_ptr->add(xid, retries);
< m_xactCyclesIDMap_ptr->add(xid, useful_cycles);
< m_xactReadSetIDMap_ptr->add(xid, readS);
< m_xactWriteSetIDMap_ptr->add(xid, writeS);
< m_xactLoadMissIDMap_ptr->add(xid, loadMisses);
< m_xactStoreMissIDMap_ptr->add(xid, storeMisses);
< m_xactInstrCountIDMap_ptr->add(xid, instrCount);
< } else {
< (m_commitIDMap_ptr->lookup(xid))++;
< (m_xactRetryIDMap_ptr->lookup(xid)) += retries;
< (m_xactCyclesIDMap_ptr->lookup(xid)) += useful_cycles;
< (m_xactReadSetIDMap_ptr->lookup(xid)) += readS;
< (m_xactWriteSetIDMap_ptr->lookup(xid)) += writeS;
< (m_xactLoadMissIDMap_ptr->lookup(xid)) += loadMisses;
< (m_xactStoreMissIDMap_ptr->lookup(xid)) += storeMisses;
< (m_xactInstrCountIDMap_ptr->lookup(xid)) += instrCount;
< }
< }
<
< void Profiler::profileBeginTransaction(NodeID id, int tid, int xid, int thread, Address pc, bool isOpen){
< //- if(PROFILE_XACT){
< if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 2)){
< const char* openStr = isOpen ? " OPEN" : " CLOSED";
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< physical_address_t myPhysPC = SIMICS_translate_address(id, pc);
< integer_t myInst = SIMICS_read_physical_memory(id, myPhysPC, 4);
< const char *myInstStr = SIMICS_disassemble_physical(id, myPhysPC);
< // The actual processor number
< int proc_no = id*RubyConfig::numberofSMTThreads() + thread;
< (* debug_cout_ptr).flags(ios::right);
< (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< (* debug_cout_ptr) << setw(ID_SPACES) << proc_no << " [" << id << "," << thread << "]" << " TID " << tid
< << " XACT BEGIN " << xid
< << " PC 0x" << hex << pc.getAddress()
< << dec
< << " *PC 0x" << hex << myInst << dec
< << " '" << myInstStr << "'"
< << openStr
< << endl;
< }
< }
<
< void Profiler::profileCommitTransaction(NodeID id, int tid, int xid, int thread, Address pc, bool isOpen){
< //- if(PROFILE_XACT){
< if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 2)){
< const char* openStr = isOpen ? " OPEN" : " CLOSED";
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< physical_address_t myPhysPC = SIMICS_translate_address(id, pc);
< integer_t myInst = SIMICS_read_physical_memory(id, myPhysPC, 4);
< const char *myInstStr = SIMICS_disassemble_physical(id, myPhysPC);
< // The actual processor number
< int proc_no = id*RubyConfig::numberofSMTThreads() + thread;
< (* debug_cout_ptr).flags(ios::right);
< (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< (* debug_cout_ptr) << setw(ID_SPACES) << proc_no << " [" << id << "," << thread << "]" << " TID " << tid
< << " XACT COMMIT " << xid
< << " PC 0x" << hex << pc.getAddress()
< << dec
< << " *PC 0x" << hex << myInst << dec
< << " '" << myInstStr << "'"
< << openStr
< << endl;
< }
<
< }
<
< // for profiling overflows
< void Profiler::profileLoadOverflow(NodeID id, int tid, int xid, int thread, Address addr, bool l1_overflow){
< //- if(PROFILE_XACT){
< if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 1)){
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< string overflow_str = " XACT LOAD L1 OVERFLOW ";
< if(!l1_overflow){
< overflow_str = " XACT LOAD L2 OVERFLOW ";
< }
< // The actual processor number
< int proc_no = id*RubyConfig::numberofSMTThreads() + thread;
< (* debug_cout_ptr).flags(ios::right);
< (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< (* debug_cout_ptr) << setw(ID_SPACES) << proc_no << " [" << id << "," << thread << "]" << " TID " << tid
< << overflow_str << xid
< << " ADDR " << addr
< << endl;
< }
< }
<
< // for profiling overflows
< void Profiler::profileStoreOverflow(NodeID id, int tid, int xid, int thread, Address addr, bool l1_overflow){
< //- if(PROFILE_XACT){
< if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 1)){
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< string overflow_str = " XACT STORE L1 OVERFLOW ";
< if(!l1_overflow){
< overflow_str = " XACT STORE L2 OVERFLOW ";
< }
< // The actual processor number
< int proc_no = id*RubyConfig::numberofSMTThreads() + thread;
< (* debug_cout_ptr).flags(ios::right);
< (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< (* debug_cout_ptr) << setw(ID_SPACES) << proc_no << " [" << id << "," << thread << "]" << " TID " << tid
< << overflow_str << xid
< << " ADDR " << addr
< << endl;
< }
< }
<
< void Profiler::profileLoadTransaction(NodeID id, int tid, int xid, int thread, Address addr, Address logicalAddress, Address pc){
< //- if(PROFILE_XACT){
< if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 3)){
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< physical_address_t myPhysPC = SIMICS_translate_address(id, pc);
< integer_t myInst = SIMICS_read_physical_memory(id, myPhysPC, 4);
< const char *myInstStr = SIMICS_disassemble_physical(id, myPhysPC);
< // The actual processor number
< int proc_no = id*RubyConfig::numberofSMTThreads() + thread;
< (* debug_cout_ptr).flags(ios::right);
< (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< (* debug_cout_ptr) << setw(ID_SPACES) << proc_no << " [" << id << "," << thread << "]" << " TID " << tid
< << " XACT LOAD " << xid
< << " " << addr
< << " VA " << logicalAddress
< << " PC " << pc
< << " *PC 0x" << hex << myInst << dec
< << " '" << myInstStr << "'"
< //<< " VAL 0x" << hex << SIMICS_read_physical_memory(proc_no, SIMICS_translate_data_address(proc_no, logicalAddress), 4) << dec
< << " VAL 0x" << hex << g_system_ptr->getDriver()->readPhysicalMemory(proc_no, addr.getAddress(), 4) << dec
< << endl;
< }
< }
<
< void Profiler::profileLoad(NodeID id, int tid, int xid, int thread, Address addr, Address logicalAddress, Address pc){
< if(PROFILE_NONXACT){
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< // The actual processor number
< int proc_no = id*RubyConfig::numberofSMTThreads() + thread;
< (* debug_cout_ptr).flags(ios::right);
< (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< (* debug_cout_ptr) << setw(ID_SPACES) << proc_no << " [" << id << "," << thread << "]" << " TID " << tid
< << " LOAD " << xid
< << " " << addr
< << " VA " << logicalAddress
< << " PC " << pc
< //<< " VAL 0x" << hex << SIMICS_read_physical_memory(proc_no, SIMICS_translate_data_address(proc_no, logicalAddress), 4) << dec
< << " VAL 0x" << hex << g_system_ptr->getDriver()->readPhysicalMemory(proc_no, addr.getAddress(), 4) << dec
< << endl;
< }
< }
<
< void Profiler::profileStoreTransaction(NodeID id, int tid, int xid, int thread, Address addr, Address logicalAddress, Address pc){
< //- if(PROFILE_XACT){
< if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 3)){
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< physical_address_t myPhysPC = SIMICS_translate_address(id, pc);
< integer_t myInst = SIMICS_read_physical_memory(id, myPhysPC, 4);
< const char *myInstStr = SIMICS_disassemble_physical(id, myPhysPC);
< // The actual processor number
< int proc_no = id*RubyConfig::numberofSMTThreads() + thread;
< (* debug_cout_ptr).flags(ios::right);
< (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< (* debug_cout_ptr) << setw(ID_SPACES) << proc_no << " [" << id << "," << thread << "]" << " TID " << tid
< << " XACT STORE " << xid
< << " " << addr
< << " VA " << logicalAddress
< << " PC " << pc
< << " *PC 0x" << hex << myInst << dec
< << " '" << myInstStr << "'"
< << endl;
< }
< }
<
< void Profiler::profileStore(NodeID id, int tid, int xid, int thread, Address addr, Address logicalAddress, Address pc){
< if(PROFILE_NONXACT){
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< // The actual processor number
< int proc_no = id*RubyConfig::numberofSMTThreads() + thread;
< (* debug_cout_ptr).flags(ios::right);
< (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< (* debug_cout_ptr) << setw(ID_SPACES) << proc_no << " [" << id << "," << thread << "]" << " TID " << tid
< << " STORE " << xid
< << " " << addr
< << " VA " << logicalAddress
< << " PC " << pc
< << endl;
< }
< }
<
< void Profiler::profileNack(NodeID id, int tid, int xid, int thread, int nacking_thread, NodeID nackedBy, Address addr, Address logicalAddress, Address pc, uint64 seq_ts, uint64 nack_ts, bool possibleCycle){
< int nid = 0; // g_system_ptr->getChip(nackedBy/RubyConfig::numberOfProcsPerChip())->getTransactionInterfaceManager(nackedBy%RubyConfig::numberOfProcsPerChip())->getXID(nacking_thread);
< assert(0);
< //- if(PROFILE_XACT){
< if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 1)){
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< physical_address_t myPhysPC = SIMICS_translate_address(id, pc);
< integer_t myInst = SIMICS_read_physical_memory(id, myPhysPC, 4);
< const char *myInstStr = SIMICS_disassemble_physical(id, myPhysPC);
< // The actual processor number
< int proc_no = id*g_NUM_SMT_THREADS + thread;
< int nack_proc_no = nackedBy*g_NUM_SMT_THREADS + nacking_thread;
< Address nack_pc = SIMICS_get_program_counter(nack_proc_no);
< (* debug_cout_ptr).flags(ios::right);
< (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< (* debug_cout_ptr) << setw(ID_SPACES) << proc_no << " [" << id << "," << thread << "]" << " TID " << tid
< << " XACT NACK " << xid
< << " by " << nack_proc_no
< << " [ " << nackedBy
< << ", " << nacking_thread
< << " ]"
< << " NID: " << nid
< << " " << addr
< << " VA " << logicalAddress
< << " PC " << pc
< << " *PC 0x" << hex << myInst << dec
< << " '" << myInstStr << "'"
< << " NackerPC " << nack_pc
< << " my_ts " << seq_ts
< << " nack_ts " << nack_ts
< << " possible_cycle " << possibleCycle
< << endl;
< }
<
< // Record nacks by xid
< if(!m_nackXIDMap_ptr->exist(xid)){
< m_nackXIDMap_ptr->add(xid, 1);
< } else {
< (m_nackXIDMap_ptr->lookup(xid))++;
< }
<
< // Record nack ID pairs by xid
< if(!m_nackXIDPairMap_ptr->exist(xid)){
< Map<int, int> * new_map = new Map<int, int>;
< new_map->add(nid, 1);
< m_nackXIDPairMap_ptr->add(xid, new_map);
< }
< else{
< // retrieve existing map
< Map<int, int> * my_map = m_nackXIDPairMap_ptr->lookup(xid);
< if(!my_map->exist(nid)){
< my_map->add(nid, 1);
< }
< else{
< (my_map->lookup(nid))++;
< }
< }
<
< // Record nacks by pc
< if(!m_nackPCMap_ptr->exist(pc)){
< m_nackPCMap_ptr->add(pc, 1);
< } else {
< (m_nackPCMap_ptr->lookup(pc))++;
< }
< }
<
< void Profiler::profileExposedConflict(NodeID id, int xid, int thread, Address addr, Address pc){
< //if(PROFILE_XACT){
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< // The actual processor number
< int proc_no = id*g_NUM_SMT_THREADS + thread;
< (* debug_cout_ptr).flags(ios::right);
< (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< (* debug_cout_ptr) << setw(ID_SPACES) << proc_no << " [" << id << "," << thread << "]" << " "
< << " EXPOSED ACTION CONFLICT " << xid
< << " ADDR " << addr
< << " PC " << pc
< << endl;
< //}
< }
<
< void Profiler::profileInferredAbort(){
< m_inferredAborts++;
< }
<
< void Profiler::profileAbortDelayConstants(int startupDelay, int perBlock){
< m_abortStarupDelay = startupDelay;
< m_abortPerBlockDelay = perBlock;
< }
<
< void Profiler::profileAbortTransaction(NodeID id, int tid, int xid, int thread, int delay, int abortingThread, int abortingProc, Address addr, Address pc){
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< int abortingXID = -1;
< // The actual processor number
< int proc_no = id*g_NUM_SMT_THREADS + thread;
< // we are passed in physical proc number. Compute logical abort proc_no
< int logical_abort_proc_no = abortingProc/g_NUM_SMT_THREADS;
< if(abortingProc >= 0){
< AbstractChip * c = g_system_ptr->getChip(logical_abort_proc_no/RubyConfig::numberOfProcsPerChip());
< abortingXID = 0; // c->getTransactionInterfaceManager(logical_abort_proc_no%RubyConfig::numberOfProcsPerChip())->getXID(abortingThread);
< assert(0);
< }
< //- if(PROFILE_XACT){
< if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 1)){
< physical_address_t myPhysPC = SIMICS_translate_address(id, pc);
< integer_t myInst = SIMICS_read_physical_memory(id, myPhysPC, 4);
< const char *myInstStr = SIMICS_disassemble_physical(id, myPhysPC);
< (* debug_cout_ptr).flags(ios::right);
< (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< (* debug_cout_ptr) << setw(ID_SPACES) << proc_no << " [" << id << "," << thread << "]" << " TID " << tid
< << " XACT ABORT " << xid
< << " caused by " << abortingProc
< << " [ " << logical_abort_proc_no
< << ", " << abortingThread
< << " ]"
< << " xid: " << abortingXID << " "
< << " address: " << addr
< << " delay: " << delay
< << " PC " << pc
< << " *PC 0x" << hex << myInst << dec
< << " '" << myInstStr << "'"
< << endl;
< }
< m_transactionAborts++;
<
< // Record aborts by xid
< if(!m_abortIDMap_ptr->exist(xid)){
< m_abortIDMap_ptr->add(xid, 1);
< } else {
< (m_abortIDMap_ptr->lookup(xid))++;
< }
< m_abortDelays.add(delay);
<
< // Record aborts by pc
< if(!m_abortPCMap_ptr->exist(pc)){
< m_abortPCMap_ptr->add(pc, 1);
< } else {
< (m_abortPCMap_ptr->lookup(pc))++;
< }
<
< // Record aborts by address
< if(!m_abortAddressMap_ptr->exist(addr)){
< m_abortAddressMap_ptr->add(addr, 1);
< } else {
< (m_abortAddressMap_ptr->lookup(addr))++;
< }
< }
<
< void Profiler::profileTransWB(){
< m_transWBs++;
< }
<
< void Profiler::profileExtraWB(){
< m_extraWBs++;
< }
<
< void Profiler::profileXactChange(int procs, int cycles){
< if(!m_procsInXactMap_ptr->exist(procs)){
< m_procsInXactMap_ptr->add(procs, cycles);
< } else {
< (m_procsInXactMap_ptr->lookup(procs)) += cycles;
< }
< }
<
< void Profiler::profileReadSet(Address addr, bool bf_filter_result, bool perfect_filter_result, NodeID id, int thread){
< // do NOT count instances when signature is empty!
< if(!bf_filter_result && !perfect_filter_result){
< m_readSetEmptyChecks++;
< return;
< }
<
< if(bf_filter_result != perfect_filter_result){
< m_readSetNoMatch++;
< /*
< // we have a false positive
< if(!m_readSetNoMatch_ptr->exist(addr)){
< m_readSetNoMatch_ptr->add(addr, 1);
< }
< else{
< (m_readSetNoMatch_ptr->lookup(addr))++;
< }
< */
< }
< else{
< m_readSetMatch++;
< /*
< // Bloom filter agrees with perfect filter
< if(!m_readSetMatch_ptr->exist(addr)){
< m_readSetMatch_ptr->add(addr, 1);
< }
< else{
< (m_readSetMatch_ptr->lookup(addr))++;
< }
< */
< }
< }
<
<
< void Profiler::profileRemoteReadSet(Address addr, bool bf_filter_result, bool perfect_filter_result, NodeID id, int thread){
< if(bf_filter_result != perfect_filter_result){
< // we have a false positive
< if(!m_remoteReadSetNoMatch_ptr->exist(addr)){
< m_remoteReadSetNoMatch_ptr->add(addr, 1);
< }
< else{
< (m_remoteReadSetNoMatch_ptr->lookup(addr))++;
< }
< }
< else{
< // Bloom filter agrees with perfect filter
< if(!m_remoteReadSetMatch_ptr->exist(addr)){
< m_remoteReadSetMatch_ptr->add(addr, 1);
< }
< else{
< (m_remoteReadSetMatch_ptr->lookup(addr))++;
< }
< }
< }
<
< void Profiler::profileWriteSet(Address addr, bool bf_filter_result, bool perfect_filter_result, NodeID id, int thread){
< // do NOT count instances when signature is empty!
< if(!bf_filter_result && !perfect_filter_result){
< m_writeSetEmptyChecks++;
< return;
< }
<
< if(bf_filter_result != perfect_filter_result){
< m_writeSetNoMatch++;
< /*
< // we have a false positive
< if(!m_writeSetNoMatch_ptr->exist(addr)){
< m_writeSetNoMatch_ptr->add(addr, 1);
< }
< else{
< (m_writeSetNoMatch_ptr->lookup(addr))++;
< }
< */
< }
< else{
< m_writeSetMatch++;
< /*
< // Bloom filter agrees with perfect filter
< if(!m_writeSetMatch_ptr->exist(addr)){
< m_writeSetMatch_ptr->add(addr, 1);
< }
< else{
< (m_writeSetMatch_ptr->lookup(addr))++;
< }
< */
< }
< }
<
<
< void Profiler::profileRemoteWriteSet(Address addr, bool bf_filter_result, bool perfect_filter_result, NodeID id, int thread){
< if(bf_filter_result != perfect_filter_result){
< // we have a false positive
< if(!m_remoteWriteSetNoMatch_ptr->exist(addr)){
< m_remoteWriteSetNoMatch_ptr->add(addr, 1);
< }
< else{
< (m_remoteWriteSetNoMatch_ptr->lookup(addr))++;
< }
< }
< else{
< // Bloom filter agrees with perfect filter
< if(!m_remoteWriteSetMatch_ptr->exist(addr)){
< m_remoteWriteSetMatch_ptr->add(addr, 1);
< }
< else{
< (m_remoteWriteSetMatch_ptr->lookup(addr))++;
< }
< }
< }
<
< void Profiler::profileTransactionLogOverflow(NodeID id, Address addr, Address pc){
< if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 1)){
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< physical_address_t myPhysPC = SIMICS_translate_address(id, pc);
< integer_t myInst = SIMICS_read_physical_memory(id, myPhysPC, 4);
< const char *myInstStr = SIMICS_disassemble_physical(id, myPhysPC);
< (* debug_cout_ptr).flags(ios::right);
< (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< (* debug_cout_ptr) << setw(ID_SPACES) << id << " "
< << " XACT LOG OVERFLOW"
< << " ADDR " << addr
< << " PC " << pc
< << " *PC 0x" << hex << myInst << dec
< << " '" << myInstStr << "'"
< << endl;
<
< }
< m_transactionLogOverflows++;
< }
<
< void Profiler::profileTransactionCacheOverflow(NodeID id, Address addr, Address pc){
< if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 1)){
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< physical_address_t myPhysPC = SIMICS_translate_address(id, pc);
< integer_t myInst = SIMICS_read_physical_memory(id, myPhysPC, 4);
< const char *myInstStr = SIMICS_disassemble_physical(id, myPhysPC);
< (* debug_cout_ptr).flags(ios::right);
< (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< (* debug_cout_ptr) << setw(ID_SPACES) << id << " "
< << " XACT CACHE OVERFLOW "
< << " ADDR " << addr
< << " PC " << pc
< << " *PC 0x" << hex << myInst << dec
< << " '" << myInstStr << "'"
< << endl;
<
< }
< m_transactionCacheOverflows++;
< }
<
< void Profiler::profileGetCPS(NodeID id, uint32 cps, Address pc){
< if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 1)){
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< physical_address_t myPhysPC = SIMICS_translate_address(id, pc);
< integer_t myInst = SIMICS_read_physical_memory(id, myPhysPC, 4);
< const char *myInstStr = SIMICS_disassemble_physical(id, myPhysPC);
<
< (* debug_cout_ptr).flags(ios::right);
< (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< (* debug_cout_ptr) << setw(ID_SPACES) << id << " "
< << " XACT GET CPS"
< << " PC " << pc
< << " *PC 0x" << hex << myInst << dec
< << " '" << myInstStr << "'"
< << " CPS 0x" << hex << cps << dec
< << endl;
< }
< }
< //---- end Transactional Memory CODE
<
<
< void Profiler::profileExceptionStart(bool xact, NodeID id, int thread, int val, int trap_level, uinteger_t pc, uinteger_t npc){
< if(xact){
< if(!m_xactExceptionMap_ptr->exist(val)){
< m_xactExceptionMap_ptr->add(val, 1);
< } else {
< (m_xactExceptionMap_ptr->lookup(val))++;
< }
< }
<
< if (!xact && !PROFILE_NONXACT) return;
<
< if(PROFILE_EXCEPTIONS){
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< // The actual processor number
< int proc_no = id*g_NUM_SMT_THREADS + thread;
<
< // get the excepting instruction
< const char * instruction;
< physical_address_t addr = SIMICS_translate_address( proc_no, Address(pc));
< if(val != 0x64 && addr != 0x0){
< // ignore instruction TLB miss
< instruction = SIMICS_disassemble_physical( proc_no, addr );
< }
<
< (* debug_cout_ptr).flags(ios::right);
< (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< (* debug_cout_ptr) << setw(ID_SPACES) << proc_no << " [" << id << "," << thread << " ]" << " ";
< if (xact)
< (* debug_cout_ptr) << " XACT Exception(";
< else
< (* debug_cout_ptr) << " Exception(";
<
< (* debug_cout_ptr) << hex << val << dec << ")_START--Trap Level " << trap_level
< << "--(PC=0x" << hex << pc << ", " << npc << ")"
< << dec;
<
< if(val != 0x64 && addr != 0x0){
< (* debug_cout_ptr) << " instruction = " << instruction;
< }
< else{
< (* debug_cout_ptr) << " instruction = INSTRUCTION TLB MISS";
< }
< (* debug_cout_ptr) << dec << endl;
< }
< }
<
< void Profiler::profileExceptionDone(bool xact, NodeID id, int thread, int val, int trap_level, uinteger_t pc, uinteger_t npc, uinteger_t tpc, uinteger_t tnpc){
< if (!xact && !PROFILE_NONXACT) return;
<
< if (PROFILE_EXCEPTIONS){
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< // The actual processor number
< int proc_no = id*g_NUM_SMT_THREADS + thread;
<
< // get the excepting instruction
< const char * instruction;
< instruction = SIMICS_disassemble_physical( proc_no, SIMICS_translate_address( proc_no, Address(pc) ) );
<
<
< (* debug_cout_ptr).flags(ios::right);
< (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< (* debug_cout_ptr) << setw(ID_SPACES) << proc_no << " [" << id << "," << thread << " ]" << " ";
< if (xact)
< (* debug_cout_ptr) << " XACT Exception(";
< else
< (* debug_cout_ptr) << " Exception(";
<
< (* debug_cout_ptr) << hex << val << dec << ")_DONE--Trap Level " << trap_level
< << "--(PC=0x" << hex << pc << ", " << npc << dec << ")"
< << "--(TPC=0x" << hex << tpc << ", " << tnpc << dec << ")"
< << endl;
< }
< }
<
< void Profiler::rubyWatch(int id){
< int rn_g1 = SIMICS_get_register_number(id, "g1");
< uint64 tr = SIMICS_read_register(id, rn_g1);
< Address watch_address = Address(tr);
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
<
< (* debug_cout_ptr).flags(ios::right);
< (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< (* debug_cout_ptr) << setw(ID_SPACES) << id << " "
< << "RUBY WATCH "
< << watch_address
< << endl;
<
< if(!m_watch_address_list_ptr->exist(watch_address)){
< m_watch_address_list_ptr->add(watch_address, 1);
< }
< }
<
< bool Profiler::watchAddress(Address addr){
< if (m_watch_address_list_ptr->exist(addr))
< return true;
< else
< return false;
< }
<
< void Profiler::profileReadFilterBitsSet(int xid, int bits, bool isCommit) {
< if (isCommit) {
< if(!m_xactReadFilterBitsSetOnCommit->exist(xid)){
< Histogram hist;
< hist.add(bits);
< m_xactReadFilterBitsSetOnCommit->add(xid, hist);
< }
< else{
< (m_xactReadFilterBitsSetOnCommit->lookup(xid)).add(bits);
< }
< } else {
< if(!m_xactReadFilterBitsSetOnAbort->exist(xid)){
< Histogram hist;
< hist.add(bits);
< m_xactReadFilterBitsSetOnAbort->add(xid, hist);
< }
< else{
< (m_xactReadFilterBitsSetOnAbort->lookup(xid)).add(bits);
< }
< }
< }
<
< void Profiler::profileWriteFilterBitsSet(int xid, int bits, bool isCommit) {
< if (isCommit) {
< if(!m_xactWriteFilterBitsSetOnCommit->exist(xid)){
< Histogram hist;
< hist.add(bits);
< m_xactWriteFilterBitsSetOnCommit->add(xid, hist);
< }
< else{
< (m_xactWriteFilterBitsSetOnCommit->lookup(xid)).add(bits);
< }
< } else {
< if(!m_xactWriteFilterBitsSetOnAbort->exist(xid)){
< Histogram hist;
< hist.add(bits);
< m_xactWriteFilterBitsSetOnAbort->add(xid, hist);
< }
< else{
< (m_xactWriteFilterBitsSetOnAbort->lookup(xid)).add(bits);
< }
< }
< }
< /*
< //gem5:Arka for decomissioning log_tm
<
< void Profiler::setXactVisualizerFile(char * filename){
< if ( (filename == NULL) ||
< (!strcmp(filename, "none")) ) {
< m_xact_visualizer_ptr = &cout;
< return;
< }
<
< if (m_xact_visualizer.is_open() ) {
< m_xact_visualizer.close ();
< }
< m_xact_visualizer.open (filename, std::ios::out);
< if (! m_xact_visualizer.is_open() ) {
< cerr << "setXactVisualizer: can't open file " << filename << endl;
< }
< else {
< m_xact_visualizer_ptr = &m_xact_visualizer;
< }
< cout << "setXactVisualizer file " << filename << endl;
< }
<
< void Profiler::printTransactionState(bool can_skip){
< if (!XACT_VISUALIZER) return;
< int num_processors = RubyConfig::numberOfProcessors() * RubyConfig::numberofSMTThreads();
<
< if (!g_system_ptr->getXactVisualizer()->existXactActivity() && can_skip)
< return;
<
< if (can_skip && ((g_eventQueue_ptr->getTime()/10000) <= m_xact_visualizer_last))
< return;
<
< Vector<char> xactStateVector = g_system_ptr->getXactVisualizer()->getTransactionStateVector();
< for (int i = 0 ; i < num_processors; i++){
< (* m_xact_visualizer_ptr) << xactStateVector[i] << " ";
< }
< (* m_xact_visualizer_ptr) << " " << g_eventQueue_ptr->getTime() << endl;
< m_xact_visualizer_last = g_eventQueue_ptr->getTime() / 10000;
< }
< */
< void Profiler::watchpointsFalsePositiveTrigger()
< {
< m_watchpointsFalsePositiveTrigger++;
< }
<
< void Profiler::watchpointsTrueTrigger()
< {
< m_watchpointsTrueTrigger++;
< }
<
< // For MemoryControl:
< void Profiler::profileMemReq(int bank) {
< m_memReq++;
< m_memBankCount[bank]++;
< }
< void Profiler::profileMemBankBusy() { m_memBankBusy++; }
< void Profiler::profileMemBusBusy() { m_memBusBusy++; }
< void Profiler::profileMemReadWriteBusy() { m_memReadWriteBusy++; }
< void Profiler::profileMemDataBusBusy() { m_memDataBusBusy++; }
< void Profiler::profileMemTfawBusy() { m_memTfawBusy++; }
< void Profiler::profileMemRefresh() { m_memRefresh++; }
< void Profiler::profileMemRead() { m_memRead++; }
< void Profiler::profileMemWrite() { m_memWrite++; }
< void Profiler::profileMemWaitCycles(int cycles) { m_memWaitCycles += cycles; }
< void Profiler::profileMemInputQ(int cycles) { m_memInputQ += cycles; }
< void Profiler::profileMemBankQ(int cycles) { m_memBankQ += cycles; }
< void Profiler::profileMemArbWait(int cycles) { m_memArbWait += cycles; }
< void Profiler::profileMemRandBusy() { m_memRandBusy++; }
< void Profiler::profileMemNotOld() { m_memNotOld++; }
<
<
< //----------- ATMTP -------------------//
<
< void Profiler::profileTransactionTCC(NodeID id, Address pc){
< if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 1)){
< physical_address_t myPhysPC = SIMICS_translate_address(id, pc);
< integer_t myInst = SIMICS_read_physical_memory(id, myPhysPC, 4);
< const char *myInstStr = SIMICS_disassemble_physical(id, myPhysPC);
<
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< cout.flags(ios::right);
< cout << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< cout << setw(ID_SPACES) << id << " "
< << " XACT Aborting! Executed TCC "
< << " PC: " << pc
< << " *PC: 0x" << hex << myInst << dec
< << " '" << myInstStr << "'"
< << endl;
< }
< m_transactionUnsupInsts++;
< }
<
< void Profiler::profileTransactionUnsupInst(NodeID id, Address pc){
< if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 1)){
< physical_address_t myPhysPC = SIMICS_translate_address(id, pc);
< integer_t myInst = SIMICS_read_physical_memory(id, myPhysPC, 4);
< const char *myInstStr = SIMICS_disassemble_physical(id, myPhysPC);
<
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< cout.flags(ios::right);
< cout << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< cout << setw(ID_SPACES) << id << " "
< << " XACT Aborting! Executed Unsupported Instruction "
< << " PC: " << pc
< << " *PC: 0x" << hex << myInst << dec
< << " '" << myInstStr << "'"
< << endl;
< }
< m_transactionUnsupInsts++;
< }
<
< void Profiler::profileTransactionSaveInst(NodeID id, Address pc){
< if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 1)){
< physical_address_t myPhysPC = SIMICS_translate_address(id, pc);
< integer_t myInst = SIMICS_read_physical_memory(id, myPhysPC, 4);
< const char *myInstStr = SIMICS_disassemble_physical(id, myPhysPC);
<
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< cout.flags(ios::right);
< cout << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< cout << setw(ID_SPACES) << id << " "
< << " XACT Aborting! Executed Save Instruction "
< << " PC: " << pc
< << " *PC: 0x" << hex << myInst << dec
< << " '" << myInstStr << "'"
< << endl;
< }
< m_transactionSaveRestAborts++;
< }
<
< void Profiler::profileTransactionRestoreInst(NodeID id, Address pc){
< if(PROFILE_XACT || (ATMTP_DEBUG_LEVEL >= 1)){
< physical_address_t myPhysPC = SIMICS_translate_address(id, pc);
< integer_t myInst = SIMICS_read_physical_memory(id, myPhysPC, 4);
< const char *myInstStr = SIMICS_disassemble_physical(id, myPhysPC);
<
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< cout.flags(ios::right);
< cout << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< cout << setw(ID_SPACES) << id << " "
< << " XACT Aborting! Executed Restore Instruction "
< << " PC: " << pc
< << " *PC: 0x" << hex << myInst << dec
< << " '" << myInstStr << "'"
< << endl;
< }
< m_transactionSaveRestAborts++;
< }
<
< void Profiler::profileTimerInterrupt(NodeID id,
< uinteger_t tick, uinteger_t tick_cmpr,
< uinteger_t stick, uinteger_t stick_cmpr,
< int trap_level,
< uinteger_t pc, uinteger_t npc,
< uinteger_t pstate, int pil){
< if (PROFILE_EXCEPTIONS) {
< const int ID_SPACES = 3;
< const int TIME_SPACES = 7;
< cout.flags(ios::right);
< cout << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
< cout << setw(ID_SPACES) << id << " ";
< cout << hex << "Timer--(Tick=0x" << tick << ", TckCmp=0x" << tick_cmpr
< << ", STick=0x" << stick << ", STickCmp=0x" << stick_cmpr
< << ")--(PC=" << pc << ", " << npc
< << dec << ")--(TL=" << trap_level << ", pil=" << pil
< << hex << ", pstate=0x" << pstate
< << dec << ")" << endl;
< }
< }