1/* 2 * Copyright (c) 1999-2013 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29/* 30 This file has been modified by Kevin Moore and Dan Nussbaum of the 31 Scalable Systems Research Group at Sun Microsystems Laboratories 32 (http://research.sun.com/scalable/) to support the Adaptive 33 Transactional Memory Test Platform (ATMTP). 34 35 Please send email to atmtp-interest@sun.com with feedback, questions, or 36 to request future announcements about ATMTP. 37 38 ---------------------------------------------------------------------- 39 40 File modification date: 2008-02-23 41 42 ---------------------------------------------------------------------- 43*/ 44
| 1/* 2 * Copyright (c) 1999-2013 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29/* 30 This file has been modified by Kevin Moore and Dan Nussbaum of the 31 Scalable Systems Research Group at Sun Microsystems Laboratories 32 (http://research.sun.com/scalable/) to support the Adaptive 33 Transactional Memory Test Platform (ATMTP). 34 35 Please send email to atmtp-interest@sun.com with feedback, questions, or 36 to request future announcements about ATMTP. 37 38 ---------------------------------------------------------------------- 39 40 File modification date: 2008-02-23 41 42 ---------------------------------------------------------------------- 43*/ 44
|
| 45#include "mem/ruby/profiler/Profiler.hh" 46
|
45#include <sys/types.h> 46#include <unistd.h> 47 48#include <algorithm> 49#include <fstream> 50 51#include "base/stl_helpers.hh" 52#include "base/str.hh" 53#include "mem/protocol/MachineType.hh" 54#include "mem/protocol/RubyRequest.hh" 55#include "mem/ruby/network/Network.hh" 56#include "mem/ruby/profiler/AddressProfiler.hh"
| 47#include <sys/types.h> 48#include <unistd.h> 49 50#include <algorithm> 51#include <fstream> 52 53#include "base/stl_helpers.hh" 54#include "base/str.hh" 55#include "mem/protocol/MachineType.hh" 56#include "mem/protocol/RubyRequest.hh" 57#include "mem/ruby/network/Network.hh" 58#include "mem/ruby/profiler/AddressProfiler.hh"
|
57#include "mem/ruby/profiler/Profiler.hh"
| 59#include "mem/ruby/system/GPUCoalescer.hh"
|
58#include "mem/ruby/system/Sequencer.hh" 59 60using namespace std; 61using m5::stl_helpers::operator<<; 62 63Profiler::Profiler(const RubySystemParams *p, RubySystem *rs) 64 : m_ruby_system(rs), m_hot_lines(p->hot_lines), 65 m_all_instructions(p->all_instructions), 66 m_num_vnets(p->number_of_virtual_networks) 67{ 68 m_address_profiler_ptr = new AddressProfiler(p->num_of_sequencers, this); 69 m_address_profiler_ptr->setHotLines(m_hot_lines); 70 m_address_profiler_ptr->setAllInstructions(m_all_instructions); 71 72 if (m_all_instructions) { 73 m_inst_profiler_ptr = new AddressProfiler(p->num_of_sequencers, this); 74 m_inst_profiler_ptr->setHotLines(m_hot_lines); 75 m_inst_profiler_ptr->setAllInstructions(m_all_instructions); 76 } 77} 78 79Profiler::~Profiler() 80{ 81} 82 83void 84Profiler::regStats(const std::string &pName) 85{ 86 if (!m_all_instructions) { 87 m_address_profiler_ptr->regStats(pName); 88 } 89 90 if (m_all_instructions) { 91 m_inst_profiler_ptr->regStats(pName); 92 } 93 94 delayHistogram 95 .init(10) 96 .name(pName + ".delayHist") 97 .desc("delay histogram for all message") 98 .flags(Stats::nozero | Stats::pdf | Stats::oneline); 99 100 for (int i = 0; i < m_num_vnets; i++) { 101 delayVCHistogram.push_back(new Stats::Histogram()); 102 delayVCHistogram[i] 103 ->init(10) 104 .name(pName + csprintf(".delayVCHist.vnet_%i", i)) 105 .desc(csprintf("delay histogram for vnet_%i", i)) 106 .flags(Stats::nozero | Stats::pdf | Stats::oneline); 107 } 108
| 60#include "mem/ruby/system/Sequencer.hh" 61 62using namespace std; 63using m5::stl_helpers::operator<<; 64 65Profiler::Profiler(const RubySystemParams *p, RubySystem *rs) 66 : m_ruby_system(rs), m_hot_lines(p->hot_lines), 67 m_all_instructions(p->all_instructions), 68 m_num_vnets(p->number_of_virtual_networks) 69{ 70 m_address_profiler_ptr = new AddressProfiler(p->num_of_sequencers, this); 71 m_address_profiler_ptr->setHotLines(m_hot_lines); 72 m_address_profiler_ptr->setAllInstructions(m_all_instructions); 73 74 if (m_all_instructions) { 75 m_inst_profiler_ptr = new AddressProfiler(p->num_of_sequencers, this); 76 m_inst_profiler_ptr->setHotLines(m_hot_lines); 77 m_inst_profiler_ptr->setAllInstructions(m_all_instructions); 78 } 79} 80 81Profiler::~Profiler() 82{ 83} 84 85void 86Profiler::regStats(const std::string &pName) 87{ 88 if (!m_all_instructions) { 89 m_address_profiler_ptr->regStats(pName); 90 } 91 92 if (m_all_instructions) { 93 m_inst_profiler_ptr->regStats(pName); 94 } 95 96 delayHistogram 97 .init(10) 98 .name(pName + ".delayHist") 99 .desc("delay histogram for all message") 100 .flags(Stats::nozero | Stats::pdf | Stats::oneline); 101 102 for (int i = 0; i < m_num_vnets; i++) { 103 delayVCHistogram.push_back(new Stats::Histogram()); 104 delayVCHistogram[i] 105 ->init(10) 106 .name(pName + csprintf(".delayVCHist.vnet_%i", i)) 107 .desc(csprintf("delay histogram for vnet_%i", i)) 108 .flags(Stats::nozero | Stats::pdf | Stats::oneline); 109 } 110
|
109 m_outstandReqHist
| 111 m_outstandReqHistSeqr
|
110 .init(10)
| 112 .init(10)
|
111 .name(pName + ".outstanding_req_hist")
| 113 .name(pName + ".outstanding_req_hist_seqr")
|
112 .desc("") 113 .flags(Stats::nozero | Stats::pdf | Stats::oneline); 114
| 114 .desc("") 115 .flags(Stats::nozero | Stats::pdf | Stats::oneline); 116
|
115 m_latencyHist
| 117 m_outstandReqHistCoalsr
|
116 .init(10)
| 118 .init(10)
|
117 .name(pName + ".latency_hist")
| 119 .name(pName + ".outstanding_req_hist_coalsr")
|
118 .desc("") 119 .flags(Stats::nozero | Stats::pdf | Stats::oneline); 120
| 120 .desc("") 121 .flags(Stats::nozero | Stats::pdf | Stats::oneline); 122
|
121 m_hitLatencyHist
| 123 m_latencyHistSeqr
|
122 .init(10)
| 124 .init(10)
|
123 .name(pName + ".hit_latency_hist")
| 125 .name(pName + ".latency_hist_seqr")
|
124 .desc("") 125 .flags(Stats::nozero | Stats::pdf | Stats::oneline); 126
| 126 .desc("") 127 .flags(Stats::nozero | Stats::pdf | Stats::oneline); 128
|
127 m_missLatencyHist
| 129 m_latencyHistCoalsr
|
128 .init(10)
| 130 .init(10)
|
129 .name(pName + ".miss_latency_hist")
| 131 .name(pName + ".latency_hist_coalsr")
|
130 .desc("") 131 .flags(Stats::nozero | Stats::pdf | Stats::oneline); 132
| 132 .desc("") 133 .flags(Stats::nozero | Stats::pdf | Stats::oneline); 134
|
| 135 m_hitLatencyHistSeqr 136 .init(10) 137 .name(pName + ".hit_latency_hist_seqr") 138 .desc("") 139 .flags(Stats::nozero | Stats::pdf | Stats::oneline); 140 141 m_missLatencyHistSeqr 142 .init(10) 143 .name(pName + ".miss_latency_hist_seqr") 144 .desc("") 145 .flags(Stats::nozero | Stats::pdf | Stats::oneline); 146 147 m_missLatencyHistCoalsr 148 .init(10) 149 .name(pName + ".miss_latency_hist_coalsr") 150 .desc("") 151 .flags(Stats::nozero | Stats::pdf | Stats::oneline); 152
|
133 for (int i = 0; i < RubyRequestType_NUM; i++) {
| 153 for (int i = 0; i < RubyRequestType_NUM; i++) {
|
134 m_typeLatencyHist.push_back(new Stats::Histogram()); 135 m_typeLatencyHist[i]
| 154 m_typeLatencyHistSeqr.push_back(new Stats::Histogram()); 155 m_typeLatencyHistSeqr[i]
|
136 ->init(10)
| 156 ->init(10)
|
137 .name(pName + csprintf(".%s.latency_hist",
| 157 .name(pName + csprintf(".%s.latency_hist_seqr",
|
138 RubyRequestType(i))) 139 .desc("") 140 .flags(Stats::nozero | Stats::pdf | Stats::oneline); 141
| 158 RubyRequestType(i))) 159 .desc("") 160 .flags(Stats::nozero | Stats::pdf | Stats::oneline); 161
|
142 m_hitTypeLatencyHist.push_back(new Stats::Histogram()); 143 m_hitTypeLatencyHist[i]
| 162 m_typeLatencyHistCoalsr.push_back(new Stats::Histogram()); 163 m_typeLatencyHistCoalsr[i]
|
144 ->init(10)
| 164 ->init(10)
|
145 .name(pName + csprintf(".%s.hit_latency_hist",
| 165 .name(pName + csprintf(".%s.latency_hist_coalsr",
|
146 RubyRequestType(i))) 147 .desc("") 148 .flags(Stats::nozero | Stats::pdf | Stats::oneline); 149
| 166 RubyRequestType(i))) 167 .desc("") 168 .flags(Stats::nozero | Stats::pdf | Stats::oneline); 169
|
150 m_missTypeLatencyHist.push_back(new Stats::Histogram()); 151 m_missTypeLatencyHist[i]
| 170 m_hitTypeLatencyHistSeqr.push_back(new Stats::Histogram()); 171 m_hitTypeLatencyHistSeqr[i]
|
152 ->init(10)
| 172 ->init(10)
|
153 .name(pName + csprintf(".%s.miss_latency_hist",
| 173 .name(pName + csprintf(".%s.hit_latency_hist_seqr",
|
154 RubyRequestType(i))) 155 .desc("") 156 .flags(Stats::nozero | Stats::pdf | Stats::oneline);
| 174 RubyRequestType(i))) 175 .desc("") 176 .flags(Stats::nozero | Stats::pdf | Stats::oneline);
|
| 177 178 m_missTypeLatencyHistSeqr.push_back(new Stats::Histogram()); 179 m_missTypeLatencyHistSeqr[i] 180 ->init(10) 181 .name(pName + csprintf(".%s.miss_latency_hist_seqr", 182 RubyRequestType(i))) 183 .desc("") 184 .flags(Stats::nozero | Stats::pdf | Stats::oneline); 185 186 m_missTypeLatencyHistCoalsr.push_back(new Stats::Histogram()); 187 m_missTypeLatencyHistCoalsr[i] 188 ->init(10) 189 .name(pName + csprintf(".%s.miss_latency_hist_coalsr", 190 RubyRequestType(i))) 191 .desc("") 192 .flags(Stats::nozero | Stats::pdf | Stats::oneline);
|
157 } 158 159 for (int i = 0; i < MachineType_NUM; i++) {
| 193 } 194 195 for (int i = 0; i < MachineType_NUM; i++) {
|
160 m_hitMachLatencyHist.push_back(new Stats::Histogram()); 161 m_hitMachLatencyHist[i]
| 196 m_hitMachLatencyHistSeqr.push_back(new Stats::Histogram()); 197 m_hitMachLatencyHistSeqr[i]
|
162 ->init(10)
| 198 ->init(10)
|
163 .name(pName + csprintf(".%s.hit_mach_latency_hist",
| 199 .name(pName + csprintf(".%s.hit_mach_latency_hist_seqr",
|
164 MachineType(i))) 165 .desc("") 166 .flags(Stats::nozero | Stats::pdf | Stats::oneline); 167
| 200 MachineType(i))) 201 .desc("") 202 .flags(Stats::nozero | Stats::pdf | Stats::oneline); 203
|
168 m_missMachLatencyHist.push_back(new Stats::Histogram()); 169 m_missMachLatencyHist[i]
| 204 m_missMachLatencyHistSeqr.push_back(new Stats::Histogram()); 205 m_missMachLatencyHistSeqr[i]
|
170 ->init(10)
| 206 ->init(10)
|
171 .name(pName + csprintf(".%s.miss_mach_latency_hist",
| 207 .name(pName + csprintf(".%s.miss_mach_latency_hist_seqr",
|
172 MachineType(i))) 173 .desc("") 174 .flags(Stats::nozero | Stats::pdf | Stats::oneline); 175
| 208 MachineType(i))) 209 .desc("") 210 .flags(Stats::nozero | Stats::pdf | Stats::oneline); 211
|
176 m_IssueToInitialDelayHist.push_back(new Stats::Histogram()); 177 m_IssueToInitialDelayHist[i]
| 212 m_missMachLatencyHistCoalsr.push_back(new Stats::Histogram()); 213 m_missMachLatencyHistCoalsr[i]
|
178 ->init(10)
| 214 ->init(10)
|
| 215 .name(pName + csprintf(".%s.miss_mach_latency_hist_coalsr", 216 MachineType(i))) 217 .desc("") 218 .flags(Stats::nozero | Stats::pdf | Stats::oneline); 219 220 m_IssueToInitialDelayHistSeqr.push_back(new Stats::Histogram()); 221 m_IssueToInitialDelayHistSeqr[i] 222 ->init(10)
|
179 .name(pName + csprintf(
| 223 .name(pName + csprintf(
|
180 ".%s.miss_latency_hist.issue_to_initial_request",
| 224 ".%s.miss_latency_hist_seqr.issue_to_initial_request",
|
181 MachineType(i))) 182 .desc("") 183 .flags(Stats::nozero | Stats::pdf | Stats::oneline); 184
| 225 MachineType(i))) 226 .desc("") 227 .flags(Stats::nozero | Stats::pdf | Stats::oneline); 228
|
185 m_InitialToForwardDelayHist.push_back(new Stats::Histogram()); 186 m_InitialToForwardDelayHist[i]
| 229 m_IssueToInitialDelayHistCoalsr.push_back(new Stats::Histogram()); 230 m_IssueToInitialDelayHistCoalsr[i]
|
187 ->init(10)
| 231 ->init(10)
|
188 .name(pName + csprintf(".%s.miss_latency_hist.initial_to_forward",
| 232 .name(pName + csprintf( 233 ".%s.miss_latency_hist_coalsr.issue_to_initial_request", 234 MachineType(i))) 235 .desc("") 236 .flags(Stats::nozero | Stats::pdf | Stats::oneline); 237 238 m_InitialToForwardDelayHistSeqr.push_back(new Stats::Histogram()); 239 m_InitialToForwardDelayHistSeqr[i] 240 ->init(10) 241 .name(pName + csprintf(".%s.miss_latency_hist_seqr.initial_to_forward",
|
189 MachineType(i))) 190 .desc("") 191 .flags(Stats::nozero | Stats::pdf | Stats::oneline); 192
| 242 MachineType(i))) 243 .desc("") 244 .flags(Stats::nozero | Stats::pdf | Stats::oneline); 245
|
193 m_ForwardToFirstResponseDelayHist.push_back(new Stats::Histogram()); 194 m_ForwardToFirstResponseDelayHist[i]
| 246 m_InitialToForwardDelayHistCoalsr.push_back(new Stats::Histogram()); 247 m_InitialToForwardDelayHistCoalsr[i]
|
195 ->init(10)
| 248 ->init(10)
|
| 249 .name(pName + csprintf(".%s.miss_latency_hist_coalsr.initial_to_forward", 250 MachineType(i))) 251 .desc("") 252 .flags(Stats::nozero | Stats::pdf | Stats::oneline); 253 254 m_ForwardToFirstResponseDelayHistSeqr.push_back(new Stats::Histogram()); 255 m_ForwardToFirstResponseDelayHistSeqr[i] 256 ->init(10)
|
196 .name(pName + csprintf(
| 257 .name(pName + csprintf(
|
197 ".%s.miss_latency_hist.forward_to_first_response",
| 258 ".%s.miss_latency_hist_seqr.forward_to_first_response",
|
198 MachineType(i))) 199 .desc("") 200 .flags(Stats::nozero | Stats::pdf | Stats::oneline); 201
| 259 MachineType(i))) 260 .desc("") 261 .flags(Stats::nozero | Stats::pdf | Stats::oneline); 262
|
202 m_FirstResponseToCompletionDelayHist.push_back(new Stats::Histogram()); 203 m_FirstResponseToCompletionDelayHist[i]
| 263 m_ForwardToFirstResponseDelayHistCoalsr.push_back(new Stats::Histogram()); 264 m_ForwardToFirstResponseDelayHistCoalsr[i]
|
204 ->init(10) 205 .name(pName + csprintf(
| 265 ->init(10) 266 .name(pName + csprintf(
|
206 ".%s.miss_latency_hist.first_response_to_completion",
| 267 ".%s.miss_latency_hist_coalsr.forward_to_first_response",
|
207 MachineType(i))) 208 .desc("") 209 .flags(Stats::nozero | Stats::pdf | Stats::oneline); 210
| 268 MachineType(i))) 269 .desc("") 270 .flags(Stats::nozero | Stats::pdf | Stats::oneline); 271
|
211 m_IncompleteTimes[i] 212 .name(pName + csprintf(".%s.incomplete_times", MachineType(i)))
| 272 m_FirstResponseToCompletionDelayHistSeqr.push_back(new Stats::Histogram()); 273 m_FirstResponseToCompletionDelayHistSeqr[i] 274 ->init(10) 275 .name(pName + csprintf( 276 ".%s.miss_latency_hist_seqr.first_response_to_completion", 277 MachineType(i)))
|
213 .desc("")
| 278 .desc("")
|
| 279 .flags(Stats::nozero | Stats::pdf | Stats::oneline); 280 281 m_FirstResponseToCompletionDelayHistCoalsr.push_back(new Stats::Histogram()); 282 m_FirstResponseToCompletionDelayHistCoalsr[i] 283 ->init(10) 284 .name(pName + csprintf( 285 ".%s.miss_latency_hist_coalsr.first_response_to_completion", 286 MachineType(i))) 287 .desc("") 288 .flags(Stats::nozero | Stats::pdf | Stats::oneline); 289 290 m_IncompleteTimesSeqr[i] 291 .name(pName + csprintf(".%s.incomplete_times_seqr", MachineType(i))) 292 .desc("")
|
214 .flags(Stats::nozero); 215 } 216 217 for (int i = 0; i < RubyRequestType_NUM; i++) {
| 293 .flags(Stats::nozero); 294 } 295 296 for (int i = 0; i < RubyRequestType_NUM; i++) {
|
218 m_hitTypeMachLatencyHist.push_back(std::vector()); 219 m_missTypeMachLatencyHist.push_back(std::vector());
| 297 m_hitTypeMachLatencyHistSeqr.push_back(std::vector<Stats::Histogram *>()); 298 m_missTypeMachLatencyHistSeqr.push_back(std::vector<Stats::Histogram *>()); 299 m_missTypeMachLatencyHistCoalsr.push_back(std::vector<Stats::Histogram *>());
|
220 221 for (int j = 0; j < MachineType_NUM; j++) {
| 300 301 for (int j = 0; j < MachineType_NUM; j++) {
|
222 m_hitTypeMachLatencyHist[i].push_back(new Stats::Histogram()); 223 m_hitTypeMachLatencyHist[i][j]
| 302 m_hitTypeMachLatencyHistSeqr[i].push_back(new Stats::Histogram()); 303 m_hitTypeMachLatencyHistSeqr[i][j]
|
224 ->init(10)
| 304 ->init(10)
|
225 .name(pName + csprintf(".%s.%s.hit_type_mach_latency_hist",
| 305 .name(pName + csprintf(".%s.%s.hit_type_mach_latency_hist_seqr",
|
226 RubyRequestType(i), MachineType(j))) 227 .desc("") 228 .flags(Stats::nozero | Stats::pdf | Stats::oneline); 229
| 306 RubyRequestType(i), MachineType(j))) 307 .desc("") 308 .flags(Stats::nozero | Stats::pdf | Stats::oneline); 309
|
230 m_missTypeMachLatencyHist[i].push_back(new Stats::Histogram()); 231 m_missTypeMachLatencyHist[i][j]
| 310 m_missTypeMachLatencyHistSeqr[i].push_back(new Stats::Histogram()); 311 m_missTypeMachLatencyHistSeqr[i][j]
|
232 ->init(10)
| 312 ->init(10)
|
233 .name(pName + csprintf(".%s.%s.miss_type_mach_latency_hist",
| 313 .name(pName + csprintf(".%s.%s.miss_type_mach_latency_hist_seqr",
|
234 RubyRequestType(i), MachineType(j))) 235 .desc("") 236 .flags(Stats::nozero | Stats::pdf | Stats::oneline);
| 314 RubyRequestType(i), MachineType(j))) 315 .desc("") 316 .flags(Stats::nozero | Stats::pdf | Stats::oneline);
|
| 317 318 m_missTypeMachLatencyHistCoalsr[i].push_back(new Stats::Histogram()); 319 m_missTypeMachLatencyHistCoalsr[i][j] 320 ->init(10) 321 .name(pName + csprintf(".%s.%s.miss_type_mach_latency_hist_coalsr", 322 RubyRequestType(i), MachineType(j))) 323 .desc("") 324 .flags(Stats::nozero | Stats::pdf | Stats::oneline);
|
237 } 238 } 239} 240 241void 242Profiler::collateStats() 243{ 244 if (!m_all_instructions) { 245 m_address_profiler_ptr->collateStats(); 246 } 247 248 if (m_all_instructions) { 249 m_inst_profiler_ptr->collateStats(); 250 } 251 252 for (uint32_t i = 0; i < MachineType_NUM; i++) { 253 for (map<uint32_t, AbstractController*>::iterator it = 254 m_ruby_system->m_abstract_controls[i].begin(); 255 it != m_ruby_system->m_abstract_controls[i].end(); ++it) { 256 257 AbstractController *ctr = (*it).second; 258 delayHistogram.add(ctr->getDelayHist()); 259 260 for (uint32_t i = 0; i < m_num_vnets; i++) { 261 delayVCHistogram[i]->add(ctr->getDelayVCHist(i)); 262 } 263 } 264 } 265 266 for (uint32_t i = 0; i < MachineType_NUM; i++) { 267 for (map<uint32_t, AbstractController*>::iterator it = 268 m_ruby_system->m_abstract_controls[i].begin(); 269 it != m_ruby_system->m_abstract_controls[i].end(); ++it) { 270 271 AbstractController *ctr = (*it).second; 272 Sequencer *seq = ctr->getCPUSequencer(); 273 if (seq != NULL) {
| 325 } 326 } 327} 328 329void 330Profiler::collateStats() 331{ 332 if (!m_all_instructions) { 333 m_address_profiler_ptr->collateStats(); 334 } 335 336 if (m_all_instructions) { 337 m_inst_profiler_ptr->collateStats(); 338 } 339 340 for (uint32_t i = 0; i < MachineType_NUM; i++) { 341 for (map<uint32_t, AbstractController*>::iterator it = 342 m_ruby_system->m_abstract_controls[i].begin(); 343 it != m_ruby_system->m_abstract_controls[i].end(); ++it) { 344 345 AbstractController *ctr = (*it).second; 346 delayHistogram.add(ctr->getDelayHist()); 347 348 for (uint32_t i = 0; i < m_num_vnets; i++) { 349 delayVCHistogram[i]->add(ctr->getDelayVCHist(i)); 350 } 351 } 352 } 353 354 for (uint32_t i = 0; i < MachineType_NUM; i++) { 355 for (map<uint32_t, AbstractController*>::iterator it = 356 m_ruby_system->m_abstract_controls[i].begin(); 357 it != m_ruby_system->m_abstract_controls[i].end(); ++it) { 358 359 AbstractController *ctr = (*it).second; 360 Sequencer *seq = ctr->getCPUSequencer(); 361 if (seq != NULL) {
|
274 m_outstandReqHist.add(seq->getOutstandReqHist());
| 362 m_outstandReqHistSeqr.add(seq->getOutstandReqHist());
|
275 }
| 363 }
|
| 364 GPUCoalescer *coal = ctr->getGPUCoalescer(); 365 if (coal != NULL) { 366 m_outstandReqHistCoalsr.add(coal->getOutstandReqHist()); 367 }
|
276 } 277 } 278 279 for (uint32_t i = 0; i < MachineType_NUM; i++) { 280 for (map<uint32_t, AbstractController*>::iterator it = 281 m_ruby_system->m_abstract_controls[i].begin(); 282 it != m_ruby_system->m_abstract_controls[i].end(); ++it) { 283 284 AbstractController *ctr = (*it).second; 285 Sequencer *seq = ctr->getCPUSequencer(); 286 if (seq != NULL) { 287 // add all the latencies
| 368 } 369 } 370 371 for (uint32_t i = 0; i < MachineType_NUM; i++) { 372 for (map<uint32_t, AbstractController*>::iterator it = 373 m_ruby_system->m_abstract_controls[i].begin(); 374 it != m_ruby_system->m_abstract_controls[i].end(); ++it) { 375 376 AbstractController *ctr = (*it).second; 377 Sequencer *seq = ctr->getCPUSequencer(); 378 if (seq != NULL) { 379 // add all the latencies
|
288 m_latencyHist.add(seq->getLatencyHist()); 289 m_hitLatencyHist.add(seq->getHitLatencyHist()); 290 m_missLatencyHist.add(seq->getMissLatencyHist());
| 380 m_latencyHistSeqr.add(seq->getLatencyHist()); 381 m_hitLatencyHistSeqr.add(seq->getHitLatencyHist()); 382 m_missLatencyHistSeqr.add(seq->getMissLatencyHist());
|
291 292 // add the per request type latencies 293 for (uint32_t j = 0; j < RubyRequestType_NUM; ++j) {
| 383 384 // add the per request type latencies 385 for (uint32_t j = 0; j < RubyRequestType_NUM; ++j) {
|
294 m_typeLatencyHist[j]
| 386 m_typeLatencyHistSeqr[j]
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295 ->add(seq->getTypeLatencyHist(j));
| 387 ->add(seq->getTypeLatencyHist(j));
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296 m_hitTypeLatencyHist[j]
| 388 m_hitTypeLatencyHistSeqr[j]
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297 ->add(seq->getHitTypeLatencyHist(j));
| 389 ->add(seq->getHitTypeLatencyHist(j));
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298 m_missTypeLatencyHist[j]
| 390 m_missTypeLatencyHistSeqr[j]
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299 ->add(seq->getMissTypeLatencyHist(j)); 300 } 301 302 // add the per machine type miss latencies 303 for (uint32_t j = 0; j < MachineType_NUM; ++j) {
| 391 ->add(seq->getMissTypeLatencyHist(j)); 392 } 393 394 // add the per machine type miss latencies 395 for (uint32_t j = 0; j < MachineType_NUM; ++j) {
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304 m_hitMachLatencyHist[j]
| 396 m_hitMachLatencyHistSeqr[j]
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305 ->add(seq->getHitMachLatencyHist(j));
| 397 ->add(seq->getHitMachLatencyHist(j));
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306 m_missMachLatencyHist[j]
| 398 m_missMachLatencyHistSeqr[j]
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307 ->add(seq->getMissMachLatencyHist(j)); 308
| 399 ->add(seq->getMissMachLatencyHist(j)); 400
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309 m_IssueToInitialDelayHist[j]->add(
| 401 m_IssueToInitialDelayHistSeqr[j]->add(
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310 seq->getIssueToInitialDelayHist(MachineType(j))); 311
| 402 seq->getIssueToInitialDelayHist(MachineType(j))); 403
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312 m_InitialToForwardDelayHist[j]->add(
| 404 m_InitialToForwardDelayHistSeqr[j]->add(
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313 seq->getInitialToForwardDelayHist(MachineType(j)));
| 405 seq->getInitialToForwardDelayHist(MachineType(j)));
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314 m_ForwardToFirstResponseDelayHist[j]->add(seq->
| 406 m_ForwardToFirstResponseDelayHistSeqr[j]->add(seq->
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315 getForwardRequestToFirstResponseHist(MachineType(j))); 316
| 407 getForwardRequestToFirstResponseHist(MachineType(j))); 408
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317 m_FirstResponseToCompletionDelayHist[j]->add(seq->
| 409 m_FirstResponseToCompletionDelayHistSeqr[j]->add(seq->
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318 getFirstResponseToCompletionDelayHist( 319 MachineType(j)));
| 410 getFirstResponseToCompletionDelayHist( 411 MachineType(j)));
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320 m_IncompleteTimes[j] +=
| 412 m_IncompleteTimesSeqr[j] +=
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321 seq->getIncompleteTimes(MachineType(j)); 322 } 323 324 // add the per (request, machine) type miss latencies 325 for (uint32_t j = 0; j < RubyRequestType_NUM; j++) { 326 for (uint32_t k = 0; k < MachineType_NUM; k++) {
| 413 seq->getIncompleteTimes(MachineType(j)); 414 } 415 416 // add the per (request, machine) type miss latencies 417 for (uint32_t j = 0; j < RubyRequestType_NUM; j++) { 418 for (uint32_t k = 0; k < MachineType_NUM; k++) {
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327 m_hitTypeMachLatencyHist[j][k]->add(
| 419 m_hitTypeMachLatencyHistSeqr[j][k]->add(
|
328 seq->getHitTypeMachLatencyHist(j,k));
| 420 seq->getHitTypeMachLatencyHist(j,k));
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329 m_missTypeMachLatencyHist[j][k]->add(
| 421 m_missTypeMachLatencyHistSeqr[j][k]->add(
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330 seq->getMissTypeMachLatencyHist(j,k)); 331 } 332 } 333 }
| 422 seq->getMissTypeMachLatencyHist(j,k)); 423 } 424 } 425 }
|
| 426 427 GPUCoalescer *coal = ctr->getGPUCoalescer(); 428 if (coal != NULL) { 429 // add all the latencies 430 m_latencyHistCoalsr.add(coal->getLatencyHist()); 431 m_missLatencyHistCoalsr.add(coal->getMissLatencyHist()); 432 433 // add the per request type latencies 434 for (uint32_t j = 0; j < RubyRequestType_NUM; ++j) { 435 m_typeLatencyHistCoalsr[j] 436 ->add(coal->getTypeLatencyHist(j)); 437 m_missTypeLatencyHistCoalsr[j] 438 ->add(coal->getMissTypeLatencyHist(j)); 439 } 440 441 // add the per machine type miss latencies 442 for (uint32_t j = 0; j < MachineType_NUM; ++j) { 443 m_missMachLatencyHistCoalsr[j] 444 ->add(coal->getMissMachLatencyHist(j)); 445 446 m_IssueToInitialDelayHistCoalsr[j]->add( 447 coal->getIssueToInitialDelayHist(MachineType(j))); 448 449 m_InitialToForwardDelayHistCoalsr[j]->add( 450 coal->getInitialToForwardDelayHist(MachineType(j))); 451 m_ForwardToFirstResponseDelayHistCoalsr[j]->add(coal-> 452 getForwardRequestToFirstResponseHist(MachineType(j))); 453 454 m_FirstResponseToCompletionDelayHistCoalsr[j]->add(coal-> 455 getFirstResponseToCompletionDelayHist( 456 MachineType(j))); 457 } 458 459 // add the per (request, machine) type miss latencies 460 for (uint32_t j = 0; j < RubyRequestType_NUM; j++) { 461 for (uint32_t k = 0; k < MachineType_NUM; k++) { 462 m_missTypeMachLatencyHistCoalsr[j][k]->add( 463 coal->getMissTypeMachLatencyHist(j,k)); 464 } 465 } 466 }
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334 } 335 } 336} 337 338void 339Profiler::addAddressTraceSample(const RubyRequest& msg, NodeID id) 340{ 341 if (msg.getType() != RubyRequestType_IFETCH) { 342 // Note: The following line should be commented out if you 343 // want to use the special profiling that is part of the GS320 344 // protocol 345 346 // NOTE: Unless PROFILE_HOT_LINES is enabled, nothing will be 347 // profiled by the AddressProfiler 348 m_address_profiler_ptr-> 349 addTraceSample(msg.getLineAddress(), msg.getProgramCounter(), 350 msg.getType(), msg.getAccessMode(), id, false); 351 } 352}
| 467 } 468 } 469} 470 471void 472Profiler::addAddressTraceSample(const RubyRequest& msg, NodeID id) 473{ 474 if (msg.getType() != RubyRequestType_IFETCH) { 475 // Note: The following line should be commented out if you 476 // want to use the special profiling that is part of the GS320 477 // protocol 478 479 // NOTE: Unless PROFILE_HOT_LINES is enabled, nothing will be 480 // profiled by the AddressProfiler 481 m_address_profiler_ptr-> 482 addTraceSample(msg.getLineAddress(), msg.getProgramCounter(), 483 msg.getType(), msg.getAccessMode(), id, false); 484 } 485}
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