1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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53
54#include "mem/ruby/profiler/Profiler.hh"
55#include "mem/ruby/profiler/CacheProfiler.hh"
56#include "mem/ruby/profiler/AddressProfiler.hh"
57#include "mem/ruby/system/System.hh"
58#include "mem/ruby/network/Network.hh"
59#include "mem/gems_common/PrioHeap.hh"
60#include "mem/protocol/CacheMsg.hh"
61#include "mem/ruby/common/Driver.hh"
62#include "mem/protocol/Protocol.hh"
63#include "mem/gems_common/util.hh"
64#include "mem/gems_common/Map.hh"
65#include "mem/ruby/common/Debug.hh"
66#include "mem/protocol/MachineType.hh"
67
68// Allows use of times() library call, which determines virtual runtime
69#include <sys/times.h>
70
71extern std::ostream * debug_cout_ptr;
72
73static double process_memory_total();
74static double process_memory_resident();
75
76Profiler::Profiler()
77 : m_conflicting_histogram(-1)
78{
79 m_requestProfileMap_ptr = new Map<string, int>;
80 m_L1D_cache_profiler_ptr = new CacheProfiler("L1D_cache");
81 m_L1I_cache_profiler_ptr = new CacheProfiler("L1I_cache");
82
83 m_L2_cache_profiler_ptr = new CacheProfiler("L2_cache");
84
85 m_address_profiler_ptr = new AddressProfiler;
86 m_inst_profiler_ptr = NULL;
87 if (PROFILE_ALL_INSTRUCTIONS) {
88 m_inst_profiler_ptr = new AddressProfiler;
89 }
90
91 m_conflicting_map_ptr = new Map<Address, Time>;
92
93 m_real_time_start_time = time(NULL); // Not reset in clearStats()
94 m_stats_period = 1000000; // Default
95 m_periodic_output_file_ptr = &cerr;
96
97 // for MemoryControl:
98 m_memReq = 0;
99 m_memBankBusy = 0;
100 m_memBusBusy = 0;
101 m_memReadWriteBusy = 0;
102 m_memDataBusBusy = 0;
103 m_memTfawBusy = 0;
104 m_memRefresh = 0;

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111 m_memRandBusy = 0;
112 m_memNotOld = 0;
113
114
115 int totalBanks = RubyConfig::banksPerRank()
116 * RubyConfig::ranksPerDimm()
117 * RubyConfig::dimmsPerChannel();
118 m_memBankCount.setSize(totalBanks);
119
120 clearStats();
121}
122
123Profiler::~Profiler()
124{
125 if (m_periodic_output_file_ptr != &cerr) {
126 delete m_periodic_output_file_ptr;
127 }
128 delete m_address_profiler_ptr;
129 delete m_L1D_cache_profiler_ptr;
130 delete m_L1I_cache_profiler_ptr;
131 delete m_L2_cache_profiler_ptr;
132 delete m_requestProfileMap_ptr;
133 delete m_conflicting_map_ptr;
134}
135
136void Profiler::wakeup()
137{
138 // FIXME - avoid the repeated code
139
140 Vector<integer_t> perProcInstructionCount;
141 perProcInstructionCount.setSize(RubyConfig::numberOfProcessors());
142
143 Vector<integer_t> perProcCycleCount;
144 perProcCycleCount.setSize(RubyConfig::numberOfProcessors());
145
146 for(int i=0; i < RubyConfig::numberOfProcessors(); i++) {
147 perProcInstructionCount[i] = g_system_ptr->getDriver()->getInstructionCount(i) - m_instructions_executed_at_start[i] + 1;
148 perProcCycleCount[i] = g_system_ptr->getDriver()->getCycleCount(i) - m_cycles_executed_at_start[i] + 1;
149 // The +1 allows us to avoid division by zero
150 }
151
152 integer_t total_misses = m_perProcTotalMisses.sum();
153 integer_t instruction_executed = perProcInstructionCount.sum();
154 integer_t cycles_executed = perProcCycleCount.sum();
155 integer_t transactions_started = m_perProcStartTransaction.sum();
156 integer_t transactions_ended = m_perProcEndTransaction.sum();
157
158 (*m_periodic_output_file_ptr) << "ruby_cycles: " << g_eventQueue_ptr->getTime()-m_ruby_start << endl;
159 (*m_periodic_output_file_ptr) << "total_misses: " << total_misses << " " << m_perProcTotalMisses << endl;
160 (*m_periodic_output_file_ptr) << "instruction_executed: " << instruction_executed << " " << perProcInstructionCount << endl;
161 (*m_periodic_output_file_ptr) << "cycles_executed: " << cycles_executed << " " << perProcCycleCount << endl;
162 (*m_periodic_output_file_ptr) << "transactions_started: " << transactions_started << " " << m_perProcStartTransaction << endl;
163 (*m_periodic_output_file_ptr) << "transactions_ended: " << transactions_ended << " " << m_perProcEndTransaction << endl;
164 (*m_periodic_output_file_ptr) << "L1TBE_usage: " << m_L1tbeProfile << endl;
165 (*m_periodic_output_file_ptr) << "L2TBE_usage: " << m_L2tbeProfile << endl;
166 (*m_periodic_output_file_ptr) << "mbytes_resident: " << process_memory_resident() << endl;
167 (*m_periodic_output_file_ptr) << "mbytes_total: " << process_memory_total() << endl;
168 if (process_memory_total() > 0) {
169 (*m_periodic_output_file_ptr) << "resident_ratio: " << process_memory_resident()/process_memory_total() << endl;
170 }
171 (*m_periodic_output_file_ptr) << "miss_latency: " << m_allMissLatencyHistogram << endl;
172
173 *m_periodic_output_file_ptr << endl;
174
175 if (PROFILE_ALL_INSTRUCTIONS) {
176 m_inst_profiler_ptr->printStats(*m_periodic_output_file_ptr);
177 }
178
179 //g_system_ptr->getNetwork()->printStats(*m_periodic_output_file_ptr);
180 g_eventQueue_ptr->scheduleEvent(this, m_stats_period);
181}
182
183void Profiler::setPeriodicStatsFile(const string& filename)

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272 Vector<integer_t> perProcInstructionCount;
273 Vector<integer_t> perProcCycleCount;
274 Vector<double> perProcCPI;
275 Vector<double> perProcMissesPerInsn;
276 Vector<double> perProcInsnPerTrans;
277 Vector<double> perProcCyclesPerTrans;
278 Vector<double> perProcMissesPerTrans;
279
280 perProcInstructionCount.setSize(RubyConfig::numberOfProcessors());
281 perProcCycleCount.setSize(RubyConfig::numberOfProcessors());
282 perProcCPI.setSize(RubyConfig::numberOfProcessors());
283 perProcMissesPerInsn.setSize(RubyConfig::numberOfProcessors());
284
285 perProcInsnPerTrans.setSize(RubyConfig::numberOfProcessors());
286 perProcCyclesPerTrans.setSize(RubyConfig::numberOfProcessors());
287 perProcMissesPerTrans.setSize(RubyConfig::numberOfProcessors());
288
289 for(int i=0; i < RubyConfig::numberOfProcessors(); i++) {
290 perProcInstructionCount[i] = g_system_ptr->getDriver()->getInstructionCount(i) - m_instructions_executed_at_start[i] + 1;
291 perProcCycleCount[i] = g_system_ptr->getDriver()->getCycleCount(i) - m_cycles_executed_at_start[i] + 1;
292 // The +1 allows us to avoid division by zero
293 perProcCPI[i] = double(ruby_cycles)/perProcInstructionCount[i];
294 perProcMissesPerInsn[i] = 1000.0 * (double(m_perProcTotalMisses[i]) / double(perProcInstructionCount[i]));
295
296 int trans = m_perProcEndTransaction[i];
297 if (trans == 0) {
298 perProcInsnPerTrans[i] = 0;
299 perProcCyclesPerTrans[i] = 0;

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304 perProcMissesPerTrans[i] = m_perProcTotalMisses[i] / double(trans);
305 }
306 }
307
308 integer_t total_misses = m_perProcTotalMisses.sum();
309 integer_t user_misses = m_perProcUserMisses.sum();
310 integer_t supervisor_misses = m_perProcSupervisorMisses.sum();
311 integer_t instruction_executed = perProcInstructionCount.sum();
312 integer_t cycles_executed = perProcCycleCount.sum();
313 integer_t transactions_started = m_perProcStartTransaction.sum();
314 integer_t transactions_ended = m_perProcEndTransaction.sum();
315
316 double instructions_per_transaction = (transactions_ended != 0) ? double(instruction_executed) / double(transactions_ended) : 0;
317 double cycles_per_transaction = (transactions_ended != 0) ? (RubyConfig::numberOfProcessors() * double(ruby_cycles)) / double(transactions_ended) : 0;
318 double misses_per_transaction = (transactions_ended != 0) ? double(total_misses) / double(transactions_ended) : 0;
319
320 out << "Total_misses: " << total_misses << endl;
321 out << "total_misses: " << total_misses << " " << m_perProcTotalMisses << endl;
322 out << "user_misses: " << user_misses << " " << m_perProcUserMisses << endl;
323 out << "supervisor_misses: " << supervisor_misses << " " << m_perProcSupervisorMisses << endl;
324 out << endl;
325 out << "instruction_executed: " << instruction_executed << " " << perProcInstructionCount << endl;
326 out << "cycles_executed: " << cycles_executed << " " << perProcCycleCount << endl;
327 out << "cycles_per_instruction: " << (RubyConfig::numberOfProcessors()*double(ruby_cycles))/double(instruction_executed) << " " << perProcCPI << endl;
328 out << "misses_per_thousand_instructions: " << 1000.0 * (double(total_misses) / double(instruction_executed)) << " " << perProcMissesPerInsn << endl;
329 out << endl;
330 out << "transactions_started: " << transactions_started << " " << m_perProcStartTransaction << endl;
331 out << "transactions_ended: " << transactions_ended << " " << m_perProcEndTransaction << endl;
332 out << "instructions_per_transaction: " << instructions_per_transaction << " " << perProcInsnPerTrans << endl;
333 out << "cycles_per_transaction: " << cycles_per_transaction << " " << perProcCyclesPerTrans << endl;
334 out << "misses_per_transaction: " << misses_per_transaction << " " << perProcMissesPerTrans << endl;
335
336 out << endl;
337
338 m_L1D_cache_profiler_ptr->printStats(out);
339 m_L1I_cache_profiler_ptr->printStats(out);
340 m_L2_cache_profiler_ptr->printStats(out);
341
342 out << endl;
343
344 if (m_memReq || m_memRefresh) { // if there's a memory controller at all
345 long long int total_stalls = m_memInputQ + m_memBankQ + m_memWaitCycles;
346 double stallsPerReq = total_stalls * 1.0 / m_memReq;
347 out << "Memory control:" << endl;
348 out << " memory_total_requests: " << m_memReq << endl; // does not include refreshes
349 out << " memory_reads: " << m_memRead << endl;
350 out << " memory_writes: " << m_memWrite << endl;
351 out << " memory_refreshes: " << m_memRefresh << endl;
352 out << " memory_total_request_delays: " << total_stalls << endl;
353 out << " memory_delays_per_request: " << stallsPerReq << endl;
354 out << " memory_delays_in_input_queue: " << m_memInputQ << endl;
355 out << " memory_delays_behind_head_of_bank_queue: " << m_memBankQ << endl;
356 out << " memory_delays_stalled_at_head_of_bank_queue: " << m_memWaitCycles << endl;
357 // Note: The following "memory stalls" entries are a breakdown of the
358 // cycles which already showed up in m_memWaitCycles. The order is
359 // significant; it is the priority of attributing the cycles.
360 // For example, bank_busy is before arbitration because if the bank was
361 // busy, we didn't even check arbitration.
362 // Note: "not old enough" means that since we grouped waiting heads-of-queues
363 // into batches to avoid starvation, a request in a newer batch
364 // didn't try to arbitrate yet because there are older requests waiting.
365 out << " memory_stalls_for_bank_busy: " << m_memBankBusy << endl;
366 out << " memory_stalls_for_random_busy: " << m_memRandBusy << endl;
367 out << " memory_stalls_for_anti_starvation: " << m_memNotOld << endl;
368 out << " memory_stalls_for_arbitration: " << m_memArbWait << endl;
369 out << " memory_stalls_for_bus: " << m_memBusBusy << endl;
370 out << " memory_stalls_for_tfaw: " << m_memTfawBusy << endl;
371 out << " memory_stalls_for_read_write_turnaround: " << m_memReadWriteBusy << endl;
372 out << " memory_stalls_for_read_read_turnaround: " << m_memDataBusBusy << endl;
373 out << " accesses_per_bank: ";
374 for (int bank=0; bank < m_memBankCount.size(); bank++) {
375 out << m_memBankCount[bank] << " ";
376 //if ((bank % 8) == 7) out << " " << endl;
377 }
378 out << endl;
379 out << endl;
380 }
381
382 if (!short_stats) {
383 out << "Busy Controller Counts:" << endl;
384 for(int i=0; i < MachineType_NUM; i++) {
385 for(int j=0; j < MachineType_base_count((MachineType)i); j++) {
386 MachineID machID;
387 machID.type = (MachineType)i;
388 machID.num = j;
389 out << machID << ":" << m_busyControllerCount[i][j] << " ";

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408 }
409
410 if (!short_stats) {
411 out << "All Non-Zero Cycle Demand Cache Accesses" << endl;
412 out << "----------------------------------------" << endl;
413 out << "miss_latency: " << m_allMissLatencyHistogram << endl;
414 for(int i=0; i<m_missLatencyHistograms.size(); i++) {
415 if (m_missLatencyHistograms[i].size() > 0) {
416 out << "miss_latency_" << CacheRequestType(i) << ": " << m_missLatencyHistograms[i] << endl;
417 }
418 }
419 for(int i=0; i<m_machLatencyHistograms.size(); i++) {
420 if (m_machLatencyHistograms[i].size() > 0) {
421 out << "miss_latency_" << GenericMachineType(i) << ": " << m_machLatencyHistograms[i] << endl;
422 }
423 }
424 out << "miss_latency_L2Miss: " << m_L2MissLatencyHistogram << endl;

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495 }
496 out << setw(11) << temp_int;
497 out << setw(14) << percent << endl;
498 }
499 out << endl;
500
501 out << "filter_action: " << m_filter_action_histogram << endl;
502
503 if (!PROFILE_ALL_INSTRUCTIONS) {
504 m_address_profiler_ptr->printStats(out);
505 }
506
507 if (PROFILE_ALL_INSTRUCTIONS) {
508 m_inst_profiler_ptr->printStats(out);
509 }
510
511 out << endl;
512 out << "Message Delayed Cycles" << endl;
513 out << "----------------------" << endl;
514 out << "Total_delay_cycles: " << m_delayedCyclesHistogram << endl;
515 out << "Total_nonPF_delay_cycles: " << m_delayedCyclesNonPFHistogram << endl;

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545
546void Profiler::clearStats()
547{
548 m_num_BA_unicasts = 0;
549 m_num_BA_broadcasts = 0;
550
551 m_ruby_start = g_eventQueue_ptr->getTime();
552
553 m_instructions_executed_at_start.setSize(RubyConfig::numberOfProcessors());
554 m_cycles_executed_at_start.setSize(RubyConfig::numberOfProcessors());
555 for (int i=0; i < RubyConfig::numberOfProcessors(); i++) {
556 if (g_system_ptr == NULL) {
557 m_instructions_executed_at_start[i] = 0;
558 m_cycles_executed_at_start[i] = 0;
559 } else {
560 m_instructions_executed_at_start[i] = g_system_ptr->getDriver()->getInstructionCount(i);
561 m_cycles_executed_at_start[i] = g_system_ptr->getDriver()->getCycleCount(i);
562 }
563 }
564
565 m_perProcTotalMisses.setSize(RubyConfig::numberOfProcessors());
566 m_perProcUserMisses.setSize(RubyConfig::numberOfProcessors());
567 m_perProcSupervisorMisses.setSize(RubyConfig::numberOfProcessors());
568 m_perProcStartTransaction.setSize(RubyConfig::numberOfProcessors());
569 m_perProcEndTransaction.setSize(RubyConfig::numberOfProcessors());
570
571 for(int i=0; i < RubyConfig::numberOfProcessors(); i++) {
572 m_perProcTotalMisses[i] = 0;
573 m_perProcUserMisses[i] = 0;
574 m_perProcSupervisorMisses[i] = 0;
575 m_perProcStartTransaction[i] = 0;
576 m_perProcEndTransaction[i] = 0;
577 }
578
579 m_busyControllerCount.setSize(MachineType_NUM); // all machines
580 for(int i=0; i < MachineType_NUM; i++) {
581 m_busyControllerCount[i].setSize(MachineType_base_count((MachineType)i));
582 for(int j=0; j < MachineType_base_count((MachineType)i); j++) {
583 m_busyControllerCount[i][j] = 0;
584 }
585 }
586 m_busyBankCount = 0;
587
588 m_delayedCyclesHistogram.clear();
589 m_delayedCyclesNonPFHistogram.clear();
590 m_delayedCyclesVCHistograms.setSize(NUMBER_OF_VIRTUAL_NETWORKS);
591 for (int i = 0; i < NUMBER_OF_VIRTUAL_NETWORKS; i++) {
592 m_delayedCyclesVCHistograms[i].clear();
593 }
594
595 m_gets_mask_prediction.clear();
596 m_getx_mask_prediction.clear();
597 m_explicit_training_mask.clear();
598
599 m_missLatencyHistograms.setSize(CacheRequestType_NUM);

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651 m_outstanding_requests.clear();
652 m_outstanding_persistent_requests.clear();
653
654 m_L1D_cache_profiler_ptr->clearStats();
655 m_L1I_cache_profiler_ptr->clearStats();
656 m_L2_cache_profiler_ptr->clearStats();
657
658 // for MemoryControl:
659 m_memReq = 0;
660 m_memBankBusy = 0;
661 m_memBusBusy = 0;
662 m_memTfawBusy = 0;
663 m_memReadWriteBusy = 0;
664 m_memDataBusBusy = 0;
665 m_memRefresh = 0;
666 m_memRead = 0;
667 m_memWrite = 0;
668 m_memWaitCycles = 0;
669 m_memInputQ = 0;
670 m_memBankQ = 0;
671 m_memArbWait = 0;
672 m_memRandBusy = 0;
673 m_memNotOld = 0;
674
675 for (int bank=0; bank < m_memBankCount.size(); bank++) {
676 m_memBankCount[bank] = 0;
677 }
678
679 // Flush the prefetches through the system - used so that there are no outstanding requests after stats are cleared
680 //g_eventQueue_ptr->triggerAllEvents();
681
682 // update the start time
683 m_ruby_start = g_eventQueue_ptr->getTime();
684}
685
686void Profiler::addPrimaryStatSample(const CacheMsg& msg, NodeID id)

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702 }
703}
704
705void Profiler::profileConflictingRequests(const Address& addr)
706{
707 assert(addr == line_address(addr));
708 Time last_time = m_ruby_start;
709 if (m_conflicting_map_ptr->exist(addr)) {
710 last_time = m_conflicting_map_ptr->lookup(addr);
711 }
712 Time current_time = g_eventQueue_ptr->getTime();
713 assert (current_time - last_time > 0);
714 m_conflicting_histogram.add(current_time - last_time);
715 m_conflicting_map_ptr->add(addr, current_time);
716}
717
718void Profiler::addSecondaryStatSample(CacheRequestType requestType, AccessModeType type, int msgSize, PrefetchBit pfBit, NodeID id)

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750
751void Profiler::addAddressTraceSample(const CacheMsg& msg, NodeID id)
752{
753 if (msg.getType() != CacheRequestType_IFETCH) {
754
755 // Note: The following line should be commented out if you want to
756 // use the special profiling that is part of the GS320 protocol
757
758 // NOTE: Unless PROFILE_HOT_LINES or PROFILE_ALL_INSTRUCTIONS are enabled, nothing will be profiled by the AddressProfiler
759 m_address_profiler_ptr->addTraceSample(msg.getAddress(), msg.getProgramCounter(), msg.getType(), msg.getAccessMode(), id, false);
760 }
761}
762
763void Profiler::profileSharing(const Address& addr, AccessType type, NodeID requestor, const Set& sharers, const Set& owner)
764{
765 Set set_contacted(owner);
766 if (type == AccessType_Write) {
767 set_contacted.addSet(sharers);

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847}
848
849void Profiler::bankBusy()
850{
851 m_busyBankCount++;
852}
853
854// non-zero cycle demand request
855void Profiler::missLatency(Time t, CacheRequestType type, GenericMachineType respondingMach)
856{
857 m_allMissLatencyHistogram.add(t);
858 m_missLatencyHistograms[type].add(t);
859 m_machLatencyHistograms[respondingMach].add(t);
860 if(respondingMach == GenericMachineType_Directory || respondingMach == GenericMachineType_NUM) {
861 m_L2MissLatencyHistogram.add(t);
862 }
863}
864
865// non-zero cycle prefetch request
866void Profiler::swPrefetchLatency(Time t, CacheRequestType type, GenericMachineType respondingMach)
867{
868 m_allSWPrefetchLatencyHistogram.add(t);
869 m_SWPrefetchLatencyHistograms[type].add(t);
870 m_SWPrefetchMachLatencyHistograms[respondingMach].add(t);
871 if(respondingMach == GenericMachineType_Directory || respondingMach == GenericMachineType_NUM) {
872 m_SWPrefetchL2MissLatencyHistogram.add(t);
873 }
874}
875
876void Profiler::profileTransition(const string& component, NodeID id, NodeID version, Address addr,
877 const string& state, const string& event,
878 const string& next_state, const string& note)
879{
880 const int EVENT_SPACES = 20;
881 const int ID_SPACES = 3;
882 const int TIME_SPACES = 7;
883 const int COMP_SPACES = 10;
884 const int STATE_SPACES = 6;
885
886 if ((g_debug_ptr->getDebugTime() > 0) &&
887 (g_eventQueue_ptr->getTime() >= g_debug_ptr->getDebugTime())) {
888 (* debug_cout_ptr).flags(ios::right);
889 (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
890 (* debug_cout_ptr) << setw(ID_SPACES) << id << " ";
891 (* debug_cout_ptr) << setw(ID_SPACES) << version << " ";
892 (* debug_cout_ptr) << setw(COMP_SPACES) << component;
893 (* debug_cout_ptr) << setw(EVENT_SPACES) << event << " ";
894 for (int i=0; i < RubyConfig::numberOfProcessors(); i++) {
895
896 if (i == id) {
897 (* debug_cout_ptr).flags(ios::right);
898 (* debug_cout_ptr) << setw(STATE_SPACES) << state;
899 (* debug_cout_ptr) << ">";
900 (* debug_cout_ptr).flags(ios::left);
901 (* debug_cout_ptr) << setw(STATE_SPACES) << next_state;
902 } else {
903 // cout << setw(STATE_SPACES) << " " << " " << setw(STATE_SPACES) << " ";
904 }
905 }
906 (* debug_cout_ptr) << " " << addr << " " << note;
907
908 (* debug_cout_ptr) << endl;
909 }
910}
911
912// Helper function
913static double process_memory_total()

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944 m_gets_mask_prediction.add(pred_set.count());
945}
946
947void Profiler::profileTrainingMask(const Set& pred_set)
948{
949 m_explicit_training_mask.add(pred_set.count());
950}
951
952// For MemoryControl:
953void Profiler::profileMemReq(int bank) {
954 m_memReq++;
955 m_memBankCount[bank]++;
956}
957
958void Profiler::profileMemBankBusy() { m_memBankBusy++; }
959void Profiler::profileMemBusBusy() { m_memBusBusy++; }
960void Profiler::profileMemReadWriteBusy() { m_memReadWriteBusy++; }
961void Profiler::profileMemDataBusBusy() { m_memDataBusBusy++; }
962void Profiler::profileMemTfawBusy() { m_memTfawBusy++; }
963void Profiler::profileMemRefresh() { m_memRefresh++; }
964void Profiler::profileMemRead() { m_memRead++; }
965void Profiler::profileMemWrite() { m_memWrite++; }
966void Profiler::profileMemWaitCycles(int cycles) { m_memWaitCycles += cycles; }
967void Profiler::profileMemInputQ(int cycles) { m_memInputQ += cycles; }
968void Profiler::profileMemBankQ(int cycles) { m_memBankQ += cycles; }
969void Profiler::profileMemArbWait(int cycles) { m_memArbWait += cycles; }
970void Profiler::profileMemRandBusy() { m_memRandBusy++; }
971void Profiler::profileMemNotOld() { m_memNotOld++; }
972
973int64 Profiler::getTotalInstructionsExecuted() const
974{
975 int64 sum = 1; // Starting at 1 allows us to avoid division by zero
976 for(int i=0; i < RubyConfig::numberOfProcessors(); i++) {
977 sum += (g_system_ptr->getDriver()->getInstructionCount(i) - m_instructions_executed_at_start[i]);
978 }
979 return sum;
980}
981
982int64 Profiler::getTotalTransactionsExecuted() const
983{
984 int64 sum = m_perProcEndTransaction.sum();
985 if (sum > 0) {

--- 23 unchanged lines hidden (view full) ---

1009 case CacheRequestType_NULL:
1010 return GenericRequestType_NULL;
1011 break;
1012 default:
1013 ERROR_MSG("Unexpected cache request type");
1014 }
1015}
1016