1/*
2 * Copyright (c) 1999-2013 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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56#include "mem/ruby/profiler/AddressProfiler.hh"
57#include "mem/ruby/profiler/Profiler.hh"
58#include "mem/ruby/system/Sequencer.hh"
59
60using namespace std;
61using m5::stl_helpers::operator<<;
62
63Profiler::Profiler(const RubySystemParams *p, RubySystem *rs)
64 : m_ruby_system(rs), m_hot_lines(p->hot_lines),
65 m_all_instructions(p->all_instructions),
66 m_num_vnets(p->number_of_virtual_networks)
67{
68 m_address_profiler_ptr = new AddressProfiler(p->num_of_sequencers, this);
69 m_address_profiler_ptr->setHotLines(m_hot_lines);
70 m_address_profiler_ptr->setAllInstructions(m_all_instructions);
71
72 if (m_all_instructions) {
73 m_inst_profiler_ptr = new AddressProfiler(p->num_of_sequencers, this);
74 m_inst_profiler_ptr->setHotLines(m_hot_lines);
75 m_inst_profiler_ptr->setAllInstructions(m_all_instructions);

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92 }
93
94 delayHistogram
95 .init(10)
96 .name(pName + ".delayHist")
97 .desc("delay histogram for all message")
98 .flags(Stats::nozero | Stats::pdf | Stats::oneline);
99
100 for (int i = 0; i < m_num_vnets; i++) {
101 delayVCHistogram.push_back(new Stats::Histogram());
102 delayVCHistogram[i]
103 ->init(10)
104 .name(pName + csprintf(".delayVCHist.vnet_%i", i))
105 .desc(csprintf("delay histogram for vnet_%i", i))
106 .flags(Stats::nozero | Stats::pdf | Stats::oneline);
107 }
108

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244 if (!m_all_instructions) {
245 m_address_profiler_ptr->collateStats();
246 }
247
248 if (m_all_instructions) {
249 m_inst_profiler_ptr->collateStats();
250 }
251
252 for (uint32_t i = 0; i < MachineType_NUM; i++) {
253 for (map<uint32_t, AbstractController*>::iterator it =
254 m_ruby_system->m_abstract_controls[i].begin();
255 it != m_ruby_system->m_abstract_controls[i].end(); ++it) {
256
257 AbstractController *ctr = (*it).second;
258 delayHistogram.add(ctr->getDelayHist());
259
260 for (uint32_t i = 0; i < m_num_vnets; i++) {
261 delayVCHistogram[i]->add(ctr->getDelayVCHist(i));
262 }
263 }
264 }
265
266 for (uint32_t i = 0; i < MachineType_NUM; i++) {
267 for (map<uint32_t, AbstractController*>::iterator it =
268 m_ruby_system->m_abstract_controls[i].begin();

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