1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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53
54#include "mem/ruby/profiler/Profiler.hh"
55#include "mem/ruby/profiler/CacheProfiler.hh"
56#include "mem/ruby/profiler/AddressProfiler.hh"
57#include "mem/ruby/system/System.hh"
58#include "mem/ruby/network/Network.hh"
59#include "mem/gems_common/PrioHeap.hh"
60#include "mem/protocol/CacheMsg.hh"
61#include "mem/protocol/Protocol.hh"
62#include "mem/gems_common/util.hh"
63#include "mem/gems_common/Map.hh"
64#include "mem/ruby/common/Debug.hh"
65#include "mem/protocol/MachineType.hh"
66
67// Allows use of times() library call, which determines virtual runtime
68#include <sys/times.h>
69
70extern std::ostream * debug_cout_ptr;
71
72static double process_memory_total();
73static double process_memory_resident();
74
75Profiler::Profiler(const string & name)
76 : m_conflicting_histogram(-1)
77{
78 m_name = name;
79 m_requestProfileMap_ptr = new Map<string, int>;
80 m_L1D_cache_profiler_ptr = new CacheProfiler("L1D_cache");
81 m_L1I_cache_profiler_ptr = new CacheProfiler("L1I_cache");
82
83 m_L2_cache_profiler_ptr = new CacheProfiler("L2_cache");
84
85 m_inst_profiler_ptr = NULL;
86 m_address_profiler_ptr = NULL;
87
88/*
89 m_address_profiler_ptr = new AddressProfiler;
90 m_inst_profiler_ptr = NULL;
91 if (m_all_instructions) {
92 m_inst_profiler_ptr = new AddressProfiler;
93 }
94*/
95 m_conflicting_map_ptr = new Map<Address, Time>;
96
97 m_real_time_start_time = time(NULL); // Not reset in clearStats()
98 m_stats_period = 1000000; // Default
99 m_periodic_output_file_ptr = &cerr;
100
101//changed by SS
102/*
103 // for MemoryControl:
104 m_memReq = 0;
105 m_memBankBusy = 0;
106 m_memBusBusy = 0;
107 m_memReadWriteBusy = 0;
108 m_memDataBusBusy = 0;
109 m_memTfawBusy = 0;
110 m_memRefresh = 0;

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117 m_memRandBusy = 0;
118 m_memNotOld = 0;
119
120
121 int totalBanks = RubyConfig::banksPerRank()
122 * RubyConfig::ranksPerDimm()
123 * RubyConfig::dimmsPerChannel();
124 m_memBankCount.setSize(totalBanks);
125*/
126}
127
128Profiler::~Profiler()
129{
130 if (m_periodic_output_file_ptr != &cerr) {
131 delete m_periodic_output_file_ptr;
132 }
133 delete m_address_profiler_ptr;
134 delete m_L1D_cache_profiler_ptr;
135 delete m_L1I_cache_profiler_ptr;
136 delete m_L2_cache_profiler_ptr;
137 delete m_requestProfileMap_ptr;
138 delete m_conflicting_map_ptr;
139}
140
141void Profiler::init(const vector<string> & argv, vector<string> memory_control_names)
142{
143 // added by SS
144 vector<string>::iterator it;
145 memory_control_profiler* mcp;
146 m_memory_control_names = memory_control_names;
147// printf ( "Here in Profiler::init \n");
148 for ( it=memory_control_names.begin() ; it < memory_control_names.end(); it++ ){
149// printf ( "Here in Profiler::init memory control name %s \n", (*it).c_str());
150 mcp = new memory_control_profiler;
151 mcp->m_memReq = 0;
152 mcp->m_memBankBusy = 0;
153 mcp->m_memBusBusy = 0;
154 mcp->m_memReadWriteBusy = 0;
155 mcp->m_memDataBusBusy = 0;
156 mcp->m_memTfawBusy = 0;
157 mcp->m_memRefresh = 0;
158 mcp->m_memRead = 0;
159 mcp->m_memWrite = 0;
160 mcp->m_memWaitCycles = 0;
161 mcp->m_memInputQ = 0;
162 mcp->m_memBankQ = 0;
163 mcp->m_memArbWait = 0;
164 mcp->m_memRandBusy = 0;
165 mcp->m_memNotOld = 0;
166
167 mcp->m_banks_per_rank = RubySystem::getMemoryControl((*it).c_str())->getBanksPerRank();
168 mcp->m_ranks_per_dimm = RubySystem::getMemoryControl((*it).c_str())->getRanksPerDimm();
169 mcp->m_dimms_per_channel = RubySystem::getMemoryControl((*it).c_str())->getDimmsPerChannel();
170
171 int totalBanks = mcp->m_banks_per_rank
172 * mcp->m_ranks_per_dimm
173 * mcp->m_dimms_per_channel;
174
175 mcp->m_memBankCount.setSize(totalBanks);
176
177 m_memory_control_profilers [(*it).c_str()] = mcp;
178 }
179
180 clearStats();
181 m_hot_lines = false;
182 m_all_instructions = false;
183
184 for (size_t i=0; i<argv.size(); i+=2) {
185 if ( argv[i] == "hot_lines") {
186 m_hot_lines = (argv[i+1]=="true");
187 } else if ( argv[i] == "all_instructions") {
188 m_all_instructions = (argv[i+1]=="true");
189 }else {
190 cerr << "WARNING: Profiler: Unkown configuration parameter: " << argv[i] << endl;
191 assert(false);
192 }
193 }
194
195 m_address_profiler_ptr = new AddressProfiler;
196 m_address_profiler_ptr -> setHotLines(m_hot_lines);
197 m_address_profiler_ptr -> setAllInstructions(m_all_instructions);
198
199 if (m_all_instructions) {
200 m_inst_profiler_ptr = new AddressProfiler;
201 m_inst_profiler_ptr -> setHotLines(m_hot_lines);
202 m_inst_profiler_ptr -> setAllInstructions(m_all_instructions);
203 }
204}
205
206void Profiler::wakeup()
207{
208 // FIXME - avoid the repeated code
209
210 Vector<integer_t> perProcInstructionCount;
211 perProcInstructionCount.setSize(RubySystem::getNumberOfSequencers());
212
213 Vector<integer_t> perProcCycleCount;
214 perProcCycleCount.setSize(RubySystem::getNumberOfSequencers());
215
216 for(int i=0; i < RubySystem::getNumberOfSequencers(); i++) {
217 perProcInstructionCount[i] = g_system_ptr->getInstructionCount(i) - m_instructions_executed_at_start[i] + 1;
218 perProcCycleCount[i] = g_system_ptr->getCycleCount(i) - m_cycles_executed_at_start[i] + 1;
219 // The +1 allows us to avoid division by zero
220 }
221
222 integer_t total_misses = m_perProcTotalMisses.sum();
223 integer_t instruction_executed = perProcInstructionCount.sum();
224 integer_t simics_cycles_executed = perProcCycleCount.sum();
225 integer_t transactions_started = m_perProcStartTransaction.sum();
226 integer_t transactions_ended = m_perProcEndTransaction.sum();
227
228 (*m_periodic_output_file_ptr) << "ruby_cycles: " << g_eventQueue_ptr->getTime()-m_ruby_start << endl;
229 (*m_periodic_output_file_ptr) << "total_misses: " << total_misses << " " << m_perProcTotalMisses << endl;
230 (*m_periodic_output_file_ptr) << "instruction_executed: " << instruction_executed << " " << perProcInstructionCount << endl;
231 (*m_periodic_output_file_ptr) << "simics_cycles_executed: " << simics_cycles_executed << " " << perProcCycleCount << endl;
232 (*m_periodic_output_file_ptr) << "transactions_started: " << transactions_started << " " << m_perProcStartTransaction << endl;
233 (*m_periodic_output_file_ptr) << "transactions_ended: " << transactions_ended << " " << m_perProcEndTransaction << endl;
234 (*m_periodic_output_file_ptr) << "L1TBE_usage: " << m_L1tbeProfile << endl;
235 (*m_periodic_output_file_ptr) << "L2TBE_usage: " << m_L2tbeProfile << endl;
236 (*m_periodic_output_file_ptr) << "mbytes_resident: " << process_memory_resident() << endl;
237 (*m_periodic_output_file_ptr) << "mbytes_total: " << process_memory_total() << endl;
238 if (process_memory_total() > 0) {
239 (*m_periodic_output_file_ptr) << "resident_ratio: " << process_memory_resident()/process_memory_total() << endl;
240 }
241 (*m_periodic_output_file_ptr) << "miss_latency: " << m_allMissLatencyHistogram << endl;
242
243 *m_periodic_output_file_ptr << endl;
244
245 if (m_all_instructions) {
246 m_inst_profiler_ptr->printStats(*m_periodic_output_file_ptr);
247 }
248
249 //g_system_ptr->getNetwork()->printStats(*m_periodic_output_file_ptr);
250 g_eventQueue_ptr->scheduleEvent(this, m_stats_period);
251}
252
253void Profiler::setPeriodicStatsFile(const string& filename)

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342 Vector<integer_t> perProcInstructionCount;
343 Vector<integer_t> perProcCycleCount;
344 Vector<double> perProcCPI;
345 Vector<double> perProcMissesPerInsn;
346 Vector<double> perProcInsnPerTrans;
347 Vector<double> perProcCyclesPerTrans;
348 Vector<double> perProcMissesPerTrans;
349
350 perProcInstructionCount.setSize(RubySystem::getNumberOfSequencers());
351 perProcCycleCount.setSize(RubySystem::getNumberOfSequencers());
352 perProcCPI.setSize(RubySystem::getNumberOfSequencers());
353 perProcMissesPerInsn.setSize(RubySystem::getNumberOfSequencers());
354
355 perProcInsnPerTrans.setSize(RubySystem::getNumberOfSequencers());
356 perProcCyclesPerTrans.setSize(RubySystem::getNumberOfSequencers());
357 perProcMissesPerTrans.setSize(RubySystem::getNumberOfSequencers());
358
359 for(int i=0; i < RubySystem::getNumberOfSequencers(); i++) {
360 perProcInstructionCount[i] = g_system_ptr->getInstructionCount(i) - m_instructions_executed_at_start[i] + 1;
361 perProcCycleCount[i] = g_system_ptr->getCycleCount(i) - m_cycles_executed_at_start[i] + 1;
362 // The +1 allows us to avoid division by zero
363 perProcCPI[i] = double(ruby_cycles)/perProcInstructionCount[i];
364 perProcMissesPerInsn[i] = 1000.0 * (double(m_perProcTotalMisses[i]) / double(perProcInstructionCount[i]));
365
366 int trans = m_perProcEndTransaction[i];
367 if (trans == 0) {
368 perProcInsnPerTrans[i] = 0;
369 perProcCyclesPerTrans[i] = 0;

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374 perProcMissesPerTrans[i] = m_perProcTotalMisses[i] / double(trans);
375 }
376 }
377
378 integer_t total_misses = m_perProcTotalMisses.sum();
379 integer_t user_misses = m_perProcUserMisses.sum();
380 integer_t supervisor_misses = m_perProcSupervisorMisses.sum();
381 integer_t instruction_executed = perProcInstructionCount.sum();
382 integer_t simics_cycles_executed = perProcCycleCount.sum();
383 integer_t transactions_started = m_perProcStartTransaction.sum();
384 integer_t transactions_ended = m_perProcEndTransaction.sum();
385
386 double instructions_per_transaction = (transactions_ended != 0) ? double(instruction_executed) / double(transactions_ended) : 0;
387 double cycles_per_transaction = (transactions_ended != 0) ? (RubySystem::getNumberOfSequencers() * double(ruby_cycles)) / double(transactions_ended) : 0;
388 double misses_per_transaction = (transactions_ended != 0) ? double(total_misses) / double(transactions_ended) : 0;
389
390 out << "Total_misses: " << total_misses << endl;
391 out << "total_misses: " << total_misses << " " << m_perProcTotalMisses << endl;
392 out << "user_misses: " << user_misses << " " << m_perProcUserMisses << endl;
393 out << "supervisor_misses: " << supervisor_misses << " " << m_perProcSupervisorMisses << endl;
394 out << endl;
395 out << "instruction_executed: " << instruction_executed << " " << perProcInstructionCount << endl;
396 out << "ruby_cycles_executed: " << simics_cycles_executed << " " << perProcCycleCount << endl;
397 out << "cycles_per_instruction: " << (RubySystem::getNumberOfSequencers()*double(ruby_cycles))/double(instruction_executed) << " " << perProcCPI << endl;
398 out << "misses_per_thousand_instructions: " << 1000.0 * (double(total_misses) / double(instruction_executed)) << " " << perProcMissesPerInsn << endl;
399 out << endl;
400 out << "transactions_started: " << transactions_started << " " << m_perProcStartTransaction << endl;
401 out << "transactions_ended: " << transactions_ended << " " << m_perProcEndTransaction << endl;
402 out << "instructions_per_transaction: " << instructions_per_transaction << " " << perProcInsnPerTrans << endl;
403 out << "cycles_per_transaction: " << cycles_per_transaction << " " << perProcCyclesPerTrans << endl;
404 out << "misses_per_transaction: " << misses_per_transaction << " " << perProcMissesPerTrans << endl;
405
406 out << endl;
407
408 m_L1D_cache_profiler_ptr->printStats(out);
409 m_L1I_cache_profiler_ptr->printStats(out);
410 m_L2_cache_profiler_ptr->printStats(out);
411
412 out << endl;
413
414 vector<string>::iterator it;
415
416 for ( it=m_memory_control_names.begin() ; it < m_memory_control_names.end(); it++ ){
417 long long int m_memReq = m_memory_control_profilers[(*it).c_str()] -> m_memReq;
418 long long int m_memRefresh = m_memory_control_profilers[(*it).c_str()] -> m_memRefresh;
419 long long int m_memInputQ = m_memory_control_profilers[(*it).c_str()] -> m_memInputQ;
420 long long int m_memBankQ = m_memory_control_profilers[(*it).c_str()] -> m_memBankQ;
421 long long int m_memWaitCycles = m_memory_control_profilers[(*it).c_str()] -> m_memWaitCycles;
422 long long int m_memRead = m_memory_control_profilers[(*it).c_str()] -> m_memRead;
423 long long int m_memWrite = m_memory_control_profilers[(*it).c_str()] -> m_memWrite;
424 long long int m_memBankBusy = m_memory_control_profilers[(*it).c_str()] -> m_memBankBusy;
425 long long int m_memRandBusy = m_memory_control_profilers[(*it).c_str()] -> m_memRandBusy;
426 long long int m_memNotOld = m_memory_control_profilers[(*it).c_str()] -> m_memNotOld;
427 long long int m_memArbWait = m_memory_control_profilers[(*it).c_str()] -> m_memArbWait;
428 long long int m_memBusBusy = m_memory_control_profilers[(*it).c_str()] -> m_memBusBusy;
429 long long int m_memTfawBusy = m_memory_control_profilers[(*it).c_str()] -> m_memTfawBusy;
430 long long int m_memReadWriteBusy = m_memory_control_profilers[(*it).c_str()] -> m_memReadWriteBusy;
431 long long int m_memDataBusBusy = m_memory_control_profilers[(*it).c_str()] -> m_memDataBusBusy;
432 Vector<long long int> m_memBankCount = m_memory_control_profilers[(*it).c_str()] -> m_memBankCount;
433
434 if (m_memReq || m_memRefresh) { // if there's a memory controller at all
435 long long int total_stalls = m_memInputQ + m_memBankQ + m_memWaitCycles;
436 double stallsPerReq = total_stalls * 1.0 / m_memReq;
437 out << "Memory control:" << endl;
438 out << " memory_total_requests: " << m_memReq << endl; // does not include refreshes
439 out << " memory_reads: " << m_memRead << endl;
440 out << " memory_writes: " << m_memWrite << endl;
441 out << " memory_refreshes: " << m_memRefresh << endl;
442 out << " memory_total_request_delays: " << total_stalls << endl;
443 out << " memory_delays_per_request: " << stallsPerReq << endl;
444 out << " memory_delays_in_input_queue: " << m_memInputQ << endl;
445 out << " memory_delays_behind_head_of_bank_queue: " << m_memBankQ << endl;
446 out << " memory_delays_stalled_at_head_of_bank_queue: " << m_memWaitCycles << endl;
447 // Note: The following "memory stalls" entries are a breakdown of the
448 // cycles which already showed up in m_memWaitCycles. The order is
449 // significant; it is the priority of attributing the cycles.
450 // For example, bank_busy is before arbitration because if the bank was
451 // busy, we didn't even check arbitration.
452 // Note: "not old enough" means that since we grouped waiting heads-of-queues
453 // into batches to avoid starvation, a request in a newer batch
454 // didn't try to arbitrate yet because there are older requests waiting.
455 out << " memory_stalls_for_bank_busy: " << m_memBankBusy << endl;
456 out << " memory_stalls_for_random_busy: " << m_memRandBusy << endl;
457 out << " memory_stalls_for_anti_starvation: " << m_memNotOld << endl;
458 out << " memory_stalls_for_arbitration: " << m_memArbWait << endl;
459 out << " memory_stalls_for_bus: " << m_memBusBusy << endl;
460 out << " memory_stalls_for_tfaw: " << m_memTfawBusy << endl;
461 out << " memory_stalls_for_read_write_turnaround: " << m_memReadWriteBusy << endl;
462 out << " memory_stalls_for_read_read_turnaround: " << m_memDataBusBusy << endl;
463 out << " accesses_per_bank: ";
464 for (int bank=0; bank < m_memBankCount.size(); bank++) {
465 out << m_memBankCount[bank] << " ";
466 //if ((bank % 8) == 7) out << " " << endl;
467 }
468 out << endl;
469 out << endl;
470 }
471 }
472 if (!short_stats) {
473 out << "Busy Controller Counts:" << endl;
474 for(int i=0; i < MachineType_NUM; i++) {
475 for(int j=0; j < MachineType_base_count((MachineType)i); j++) {
476 MachineID machID;
477 machID.type = (MachineType)i;
478 machID.num = j;
479 out << machID << ":" << m_busyControllerCount[i][j] << " ";

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498 }
499
500 if (!short_stats) {
501 out << "All Non-Zero Cycle Demand Cache Accesses" << endl;
502 out << "----------------------------------------" << endl;
503 out << "miss_latency: " << m_allMissLatencyHistogram << endl;
504 for(int i=0; i<m_missLatencyHistograms.size(); i++) {
505 if (m_missLatencyHistograms[i].size() > 0) {
506 out << "miss_latency_" << RubyRequestType(i) << ": " << m_missLatencyHistograms[i] << endl;
507 }
508 }
509 for(int i=0; i<m_machLatencyHistograms.size(); i++) {
510 if (m_machLatencyHistograms[i].size() > 0) {
511 out << "miss_latency_" << GenericMachineType(i) << ": " << m_machLatencyHistograms[i] << endl;
512 }
513 }
514 out << "miss_latency_L2Miss: " << m_L2MissLatencyHistogram << endl;

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585 }
586 out << setw(11) << temp_int;
587 out << setw(14) << percent << endl;
588 }
589 out << endl;
590
591 out << "filter_action: " << m_filter_action_histogram << endl;
592
593 if (!m_all_instructions) {
594 m_address_profiler_ptr->printStats(out);
595 }
596
597 if (m_all_instructions) {
598 m_inst_profiler_ptr->printStats(out);
599 }
600
601 out << endl;
602 out << "Message Delayed Cycles" << endl;
603 out << "----------------------" << endl;
604 out << "Total_delay_cycles: " << m_delayedCyclesHistogram << endl;
605 out << "Total_nonPF_delay_cycles: " << m_delayedCyclesNonPFHistogram << endl;

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635
636void Profiler::clearStats()
637{
638 m_num_BA_unicasts = 0;
639 m_num_BA_broadcasts = 0;
640
641 m_ruby_start = g_eventQueue_ptr->getTime();
642
643 m_instructions_executed_at_start.setSize(RubySystem::getNumberOfSequencers());
644 m_cycles_executed_at_start.setSize(RubySystem::getNumberOfSequencers());
645 for (int i=0; i < RubySystem::getNumberOfSequencers(); i++) {
646 if (g_system_ptr == NULL) {
647 m_instructions_executed_at_start[i] = 0;
648 m_cycles_executed_at_start[i] = 0;
649 } else {
650 m_instructions_executed_at_start[i] = g_system_ptr->getInstructionCount(i);
651 m_cycles_executed_at_start[i] = g_system_ptr->getCycleCount(i);
652 }
653 }
654
655 m_perProcTotalMisses.setSize(RubySystem::getNumberOfSequencers());
656 m_perProcUserMisses.setSize(RubySystem::getNumberOfSequencers());
657 m_perProcSupervisorMisses.setSize(RubySystem::getNumberOfSequencers());
658 m_perProcStartTransaction.setSize(RubySystem::getNumberOfSequencers());
659 m_perProcEndTransaction.setSize(RubySystem::getNumberOfSequencers());
660
661 for(int i=0; i < RubySystem::getNumberOfSequencers(); i++) {
662 m_perProcTotalMisses[i] = 0;
663 m_perProcUserMisses[i] = 0;
664 m_perProcSupervisorMisses[i] = 0;
665 m_perProcStartTransaction[i] = 0;
666 m_perProcEndTransaction[i] = 0;
667 }
668
669 m_busyControllerCount.setSize(MachineType_NUM); // all machines
670 for(int i=0; i < MachineType_NUM; i++) {
671 m_busyControllerCount[i].setSize(MachineType_base_count((MachineType)i));
672 for(int j=0; j < MachineType_base_count((MachineType)i); j++) {
673 m_busyControllerCount[i][j] = 0;
674 }
675 }
676 m_busyBankCount = 0;
677
678 m_delayedCyclesHistogram.clear();
679 m_delayedCyclesNonPFHistogram.clear();
680 m_delayedCyclesVCHistograms.setSize(RubySystem::getNetwork()->getNumberOfVirtualNetworks());
681 for (int i = 0; i < RubySystem::getNetwork()->getNumberOfVirtualNetworks(); i++) {
682 m_delayedCyclesVCHistograms[i].clear();
683 }
684
685 m_gets_mask_prediction.clear();
686 m_getx_mask_prediction.clear();
687 m_explicit_training_mask.clear();
688
689 m_missLatencyHistograms.setSize(CacheRequestType_NUM);

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741 m_outstanding_requests.clear();
742 m_outstanding_persistent_requests.clear();
743
744 m_L1D_cache_profiler_ptr->clearStats();
745 m_L1I_cache_profiler_ptr->clearStats();
746 m_L2_cache_profiler_ptr->clearStats();
747
748 // for MemoryControl:
749/*
750 m_memReq = 0;
751 m_memBankBusy = 0;
752 m_memBusBusy = 0;
753 m_memTfawBusy = 0;
754 m_memReadWriteBusy = 0;
755 m_memDataBusBusy = 0;
756 m_memRefresh = 0;
757 m_memRead = 0;
758 m_memWrite = 0;
759 m_memWaitCycles = 0;
760 m_memInputQ = 0;
761 m_memBankQ = 0;
762 m_memArbWait = 0;
763 m_memRandBusy = 0;
764 m_memNotOld = 0;
765
766 for (int bank=0; bank < m_memBankCount.size(); bank++) {
767 m_memBankCount[bank] = 0;
768 }
769*/
770//added by SS
771 vector<string>::iterator it;
772
773 for ( it=m_memory_control_names.begin() ; it < m_memory_control_names.end(); it++ ){
774 m_memory_control_profilers[(*it).c_str()] -> m_memReq = 0;
775 m_memory_control_profilers[(*it).c_str()] -> m_memBankBusy = 0;
776 m_memory_control_profilers[(*it).c_str()] -> m_memBusBusy = 0;
777 m_memory_control_profilers[(*it).c_str()] -> m_memTfawBusy = 0;
778 m_memory_control_profilers[(*it).c_str()] -> m_memReadWriteBusy = 0;
779 m_memory_control_profilers[(*it).c_str()] -> m_memDataBusBusy = 0;
780 m_memory_control_profilers[(*it).c_str()] -> m_memRefresh = 0;
781 m_memory_control_profilers[(*it).c_str()] -> m_memRead = 0;
782 m_memory_control_profilers[(*it).c_str()] -> m_memWrite = 0;
783 m_memory_control_profilers[(*it).c_str()] -> m_memWaitCycles = 0;
784 m_memory_control_profilers[(*it).c_str()] -> m_memInputQ = 0;
785 m_memory_control_profilers[(*it).c_str()] -> m_memBankQ = 0;
786 m_memory_control_profilers[(*it).c_str()] -> m_memArbWait = 0;
787 m_memory_control_profilers[(*it).c_str()] -> m_memRandBusy = 0;
788 m_memory_control_profilers[(*it).c_str()] -> m_memNotOld = 0;
789
790 for (int bank=0; bank < m_memory_control_profilers[(*it).c_str()] -> m_memBankCount.size(); bank++) {
791 m_memory_control_profilers[(*it).c_str()] -> m_memBankCount[bank] = 0;
792 }
793 }
794 // Flush the prefetches through the system - used so that there are no outstanding requests after stats are cleared
795 //g_eventQueue_ptr->triggerAllEvents();
796
797 // update the start time
798 m_ruby_start = g_eventQueue_ptr->getTime();
799}
800
801void Profiler::addPrimaryStatSample(const CacheMsg& msg, NodeID id)

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817 }
818}
819
820void Profiler::profileConflictingRequests(const Address& addr)
821{
822 assert(addr == line_address(addr));
823 Time last_time = m_ruby_start;
824 if (m_conflicting_map_ptr->exist(addr)) {
825 Time last_time = m_conflicting_map_ptr->lookup(addr);
826 }
827 Time current_time = g_eventQueue_ptr->getTime();
828 assert (current_time - last_time > 0);
829 m_conflicting_histogram.add(current_time - last_time);
830 m_conflicting_map_ptr->add(addr, current_time);
831}
832
833void Profiler::addSecondaryStatSample(CacheRequestType requestType, AccessModeType type, int msgSize, PrefetchBit pfBit, NodeID id)

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865
866void Profiler::addAddressTraceSample(const CacheMsg& msg, NodeID id)
867{
868 if (msg.getType() != CacheRequestType_IFETCH) {
869
870 // Note: The following line should be commented out if you want to
871 // use the special profiling that is part of the GS320 protocol
872
873 // NOTE: Unless PROFILE_HOT_LINES or RubyConfig::getProfileAllInstructions() are enabled, nothing will be profiled by the AddressProfiler
874 m_address_profiler_ptr->addTraceSample(msg.getLineAddress(), msg.getProgramCounter(), msg.getType(), msg.getAccessMode(), id, false);
875 }
876}
877
878void Profiler::profileSharing(const Address& addr, AccessType type, NodeID requestor, const Set& sharers, const Set& owner)
879{
880 Set set_contacted(owner);
881 if (type == AccessType_Write) {
882 set_contacted.addSet(sharers);

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962}
963
964void Profiler::bankBusy()
965{
966 m_busyBankCount++;
967}
968
969// non-zero cycle demand request
970void Profiler::missLatency(Time t, RubyRequestType type)
971{
972 m_allMissLatencyHistogram.add(t);
973 m_missLatencyHistograms[type].add(t);
974 /*
975 m_machLatencyHistograms[respondingMach].add(t);
976 if(respondingMach == GenericMachineType_Directory || respondingMach == GenericMachineType_NUM) {
977 m_L2MissLatencyHistogram.add(t);
978 }
979 */
980}
981
982// non-zero cycle prefetch request
983void Profiler::swPrefetchLatency(Time t, CacheRequestType type, GenericMachineType respondingMach)
984{
985 m_allSWPrefetchLatencyHistogram.add(t);
986 m_SWPrefetchLatencyHistograms[type].add(t);
987 m_SWPrefetchMachLatencyHistograms[respondingMach].add(t);
988 if(respondingMach == GenericMachineType_Directory || respondingMach == GenericMachineType_NUM) {
989 m_SWPrefetchL2MissLatencyHistogram.add(t);
990 }
991}
992
993void Profiler::profileTransition(const string& component, NodeID version, Address addr,
994 const string& state, const string& event,
995 const string& next_state, const string& note)
996{
997 const int EVENT_SPACES = 20;
998 const int ID_SPACES = 3;
999 const int TIME_SPACES = 7;
1000 const int COMP_SPACES = 10;
1001 const int STATE_SPACES = 6;
1002
1003 if ((g_debug_ptr->getDebugTime() > 0) &&
1004 (g_eventQueue_ptr->getTime() >= g_debug_ptr->getDebugTime())) {
1005 (* debug_cout_ptr).flags(ios::right);
1006 (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
1007 (* debug_cout_ptr) << setw(ID_SPACES) << version << " ";
1008 (* debug_cout_ptr) << setw(COMP_SPACES) << component;
1009 (* debug_cout_ptr) << setw(EVENT_SPACES) << event << " ";
1010
1011 (* debug_cout_ptr).flags(ios::right);
1012 (* debug_cout_ptr) << setw(STATE_SPACES) << state;
1013 (* debug_cout_ptr) << ">";
1014 (* debug_cout_ptr).flags(ios::left);
1015 (* debug_cout_ptr) << setw(STATE_SPACES) << next_state;
1016
1017 (* debug_cout_ptr) << " " << addr << " " << note;
1018
1019 (* debug_cout_ptr) << endl;
1020 }
1021}
1022
1023// Helper function
1024static double process_memory_total()

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1055 m_gets_mask_prediction.add(pred_set.count());
1056}
1057
1058void Profiler::profileTrainingMask(const Set& pred_set)
1059{
1060 m_explicit_training_mask.add(pred_set.count());
1061}
1062
1063int64 Profiler::getTotalInstructionsExecuted() const
1064{
1065 int64 sum = 1; // Starting at 1 allows us to avoid division by zero
1066 for(int i=0; i < RubySystem::getNumberOfSequencers(); i++) {
1067 sum += (g_system_ptr->getInstructionCount(i) - m_instructions_executed_at_start[i]);
1068 }
1069 return sum;
1070}
1071
1072int64 Profiler::getTotalTransactionsExecuted() const
1073{
1074 int64 sum = m_perProcEndTransaction.sum();
1075 if (sum > 0) {

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1099 case CacheRequestType_NULL:
1100 return GenericRequestType_NULL;
1101 break;
1102 default:
1103 ERROR_MSG("Unexpected cache request type");
1104 }
1105}
1106
1107void Profiler::rubyWatch(int id){
1108 int rn_g1 = 0;//SIMICS_get_register_number(id, "g1");
1109 uint64 tr = 0;//SIMICS_read_register(id, rn_g1);
1110 Address watch_address = Address(tr);
1111 const int ID_SPACES = 3;
1112 const int TIME_SPACES = 7;
1113
1114 (* debug_cout_ptr).flags(ios::right);
1115 (* debug_cout_ptr) << setw(TIME_SPACES) << g_eventQueue_ptr->getTime() << " ";
1116 (* debug_cout_ptr) << setw(ID_SPACES) << id << " "
1117 << "RUBY WATCH "
1118 << watch_address
1119 << endl;
1120
1121 if(!m_watch_address_list_ptr->exist(watch_address)){
1122 m_watch_address_list_ptr->add(watch_address, 1);
1123 }
1124}
1125
1126bool Profiler::watchAddress(Address addr){
1127 if (m_watch_address_list_ptr->exist(addr))
1128 return true;
1129 else
1130 return false;
1131}
1132
1133// For MemoryControl:
1134void Profiler::profileMemReq(string name, int bank) {
1135// printf("name is %s", name.c_str());
1136 assert(m_memory_control_profilers.count(name) == 1);
1137 m_memory_control_profilers[name] -> m_memReq++;
1138 m_memory_control_profilers[name] -> m_memBankCount[bank]++;
1139}
1140void Profiler::profileMemBankBusy(string name) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memBankBusy++; }
1141void Profiler::profileMemBusBusy(string name) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memBusBusy++; }
1142void Profiler::profileMemReadWriteBusy(string name) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memReadWriteBusy++; }
1143void Profiler::profileMemDataBusBusy(string name) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memDataBusBusy++; }
1144void Profiler::profileMemTfawBusy(string name) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memTfawBusy++; }
1145void Profiler::profileMemRefresh(string name) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memRefresh++; }
1146void Profiler::profileMemRead(string name) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memRead++; }
1147void Profiler::profileMemWrite(string name) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memWrite++; }
1148void Profiler::profileMemWaitCycles(string name, int cycles) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memWaitCycles += cycles; }
1149void Profiler::profileMemInputQ(string name, int cycles) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memInputQ += cycles; }
1150void Profiler::profileMemBankQ(string name, int cycles) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memBankQ += cycles; }
1151void Profiler::profileMemArbWait(string name, int cycles) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memArbWait += cycles; }
1152void Profiler::profileMemRandBusy(string name) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memRandBusy++; }
1153void Profiler::profileMemNotOld(string name) { assert(m_memory_control_profilers.count(name) == 1); m_memory_control_profilers[name] -> m_memNotOld++; }
1154