AccessTraceForAddress.cc (6154:6bb54dcb940e) AccessTraceForAddress.cc (7048:2ab58c54de63)
1
2/*
3 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;

--- 12 unchanged lines hidden (view full) ---

22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 12 unchanged lines hidden (view full) ---

21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
30/*
31 * $Id$
32 *
33 */
34
35#include "mem/ruby/profiler/AccessTraceForAddress.hh"
36#include "mem/ruby/common/Histogram.hh"
29#include "mem/ruby/common/Histogram.hh"
30#include "mem/ruby/profiler/AccessTraceForAddress.hh"
37
38AccessTraceForAddress::AccessTraceForAddress()
39{
31
32AccessTraceForAddress::AccessTraceForAddress()
33{
40 m_histogram_ptr = NULL;
34 m_histogram_ptr = NULL;
41}
42
43AccessTraceForAddress::AccessTraceForAddress(const Address& addr)
44{
35}
36
37AccessTraceForAddress::AccessTraceForAddress(const Address& addr)
38{
45 m_addr = addr;
46 m_total = 0;
47 m_loads = 0;
48 m_stores = 0;
49 m_atomics = 0;
50 m_user = 0;
51 m_sharing = 0;
52 m_histogram_ptr = NULL;
39 m_addr = addr;
40 m_total = 0;
41 m_loads = 0;
42 m_stores = 0;
43 m_atomics = 0;
44 m_user = 0;
45 m_sharing = 0;
46 m_histogram_ptr = NULL;
53}
54
55AccessTraceForAddress::~AccessTraceForAddress()
56{
47}
48
49AccessTraceForAddress::~AccessTraceForAddress()
50{
57 if (m_histogram_ptr != NULL) {
58 delete m_histogram_ptr;
59 m_histogram_ptr = NULL;
60 }
51 if (m_histogram_ptr != NULL) {
52 delete m_histogram_ptr;
53 m_histogram_ptr = NULL;
54 }
61}
62
55}
56
63void AccessTraceForAddress::print(ostream& out) const
57void
58AccessTraceForAddress::print(ostream& out) const
64{
59{
65 out << m_addr;
60 out << m_addr;
66
61
67 if (m_histogram_ptr == NULL) {
68 out << " " << m_total;
69 out << " | " << m_loads;
70 out << " " << m_stores;
71 out << " " << m_atomics;
72 out << " | " << m_user;
73 out << " " << m_total-m_user;
74 out << " | " << m_sharing;
75 out << " | " << m_touched_by.count();
76 } else {
77 assert(m_total == 0);
78 out << " " << (*m_histogram_ptr);
79 }
62 if (m_histogram_ptr == NULL) {
63 out << " " << m_total;
64 out << " | " << m_loads;
65 out << " " << m_stores;
66 out << " " << m_atomics;
67 out << " | " << m_user;
68 out << " " << m_total-m_user;
69 out << " | " << m_sharing;
70 out << " | " << m_touched_by.count();
71 } else {
72 assert(m_total == 0);
73 out << " " << (*m_histogram_ptr);
74 }
80}
81
75}
76
82void AccessTraceForAddress::update(CacheRequestType type, AccessModeType access_mode, NodeID cpu, bool sharing_miss)
77void
78AccessTraceForAddress::update(CacheRequestType type,
79 AccessModeType access_mode, NodeID cpu,
80 bool sharing_miss)
83{
81{
84 m_touched_by.add(cpu);
85 m_total++;
86 if(type == CacheRequestType_ATOMIC) {
87 m_atomics++;
88 } else if(type == CacheRequestType_LD){
89 m_loads++;
90 } else if (type == CacheRequestType_ST){
91 m_stores++;
92 } else {
93 // ERROR_MSG("Trying to add invalid access to trace");
94 }
82 m_touched_by.add(cpu);
83 m_total++;
84 if(type == CacheRequestType_ATOMIC) {
85 m_atomics++;
86 } else if(type == CacheRequestType_LD){
87 m_loads++;
88 } else if (type == CacheRequestType_ST){
89 m_stores++;
90 } else {
91 // ERROR_MSG("Trying to add invalid access to trace");
92 }
95
93
96 if (access_mode == AccessModeType_UserMode) {
97 m_user++;
98 }
94 if (access_mode == AccessModeType_UserMode) {
95 m_user++;
96 }
99
97
100 if (sharing_miss) {
101 m_sharing++;
102 }
98 if (sharing_miss) {
99 m_sharing++;
100 }
103}
104
101}
102
105int AccessTraceForAddress::getTotal() const
103int
104AccessTraceForAddress::getTotal() const
106{
105{
107 if (m_histogram_ptr == NULL) {
108 return m_total;
109 } else {
110 return m_histogram_ptr->getTotal();
111 }
106 if (m_histogram_ptr == NULL) {
107 return m_total;
108 } else {
109 return m_histogram_ptr->getTotal();
110 }
112}
113
111}
112
114void AccessTraceForAddress::addSample(int value)
113void
114AccessTraceForAddress::addSample(int value)
115{
115{
116 assert(m_total == 0);
117 if (m_histogram_ptr == NULL) {
118 m_histogram_ptr = new Histogram;
119 }
120 m_histogram_ptr->add(value);
116 assert(m_total == 0);
117 if (m_histogram_ptr == NULL) {
118 m_histogram_ptr = new Histogram;
119 }
120 m_histogram_ptr->add(value);
121}
121}
122
123bool node_less_then_eq(const AccessTraceForAddress* n1, const AccessTraceForAddress* n2)
124{
125 return (n1->getTotal() > n2->getTotal());
126}