1d0
<
30,35d28
< /*
< * $Id$
< *
< */
<
< #include "mem/ruby/profiler/AccessTraceForAddress.hh"
36a30
> #include "mem/ruby/profiler/AccessTraceForAddress.hh"
40c34
< m_histogram_ptr = NULL;
---
> m_histogram_ptr = NULL;
45,52c39,46
< m_addr = addr;
< m_total = 0;
< m_loads = 0;
< m_stores = 0;
< m_atomics = 0;
< m_user = 0;
< m_sharing = 0;
< m_histogram_ptr = NULL;
---
> m_addr = addr;
> m_total = 0;
> m_loads = 0;
> m_stores = 0;
> m_atomics = 0;
> m_user = 0;
> m_sharing = 0;
> m_histogram_ptr = NULL;
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< if (m_histogram_ptr != NULL) {
< delete m_histogram_ptr;
< m_histogram_ptr = NULL;
< }
---
> if (m_histogram_ptr != NULL) {
> delete m_histogram_ptr;
> m_histogram_ptr = NULL;
> }
63c57,58
< void AccessTraceForAddress::print(ostream& out) const
---
> void
> AccessTraceForAddress::print(ostream& out) const
65c60
< out << m_addr;
---
> out << m_addr;
67,79c62,74
< if (m_histogram_ptr == NULL) {
< out << " " << m_total;
< out << " | " << m_loads;
< out << " " << m_stores;
< out << " " << m_atomics;
< out << " | " << m_user;
< out << " " << m_total-m_user;
< out << " | " << m_sharing;
< out << " | " << m_touched_by.count();
< } else {
< assert(m_total == 0);
< out << " " << (*m_histogram_ptr);
< }
---
> if (m_histogram_ptr == NULL) {
> out << " " << m_total;
> out << " | " << m_loads;
> out << " " << m_stores;
> out << " " << m_atomics;
> out << " | " << m_user;
> out << " " << m_total-m_user;
> out << " | " << m_sharing;
> out << " | " << m_touched_by.count();
> } else {
> assert(m_total == 0);
> out << " " << (*m_histogram_ptr);
> }
82c77,80
< void AccessTraceForAddress::update(CacheRequestType type, AccessModeType access_mode, NodeID cpu, bool sharing_miss)
---
> void
> AccessTraceForAddress::update(CacheRequestType type,
> AccessModeType access_mode, NodeID cpu,
> bool sharing_miss)
84,94c82,92
< m_touched_by.add(cpu);
< m_total++;
< if(type == CacheRequestType_ATOMIC) {
< m_atomics++;
< } else if(type == CacheRequestType_LD){
< m_loads++;
< } else if (type == CacheRequestType_ST){
< m_stores++;
< } else {
< // ERROR_MSG("Trying to add invalid access to trace");
< }
---
> m_touched_by.add(cpu);
> m_total++;
> if(type == CacheRequestType_ATOMIC) {
> m_atomics++;
> } else if(type == CacheRequestType_LD){
> m_loads++;
> } else if (type == CacheRequestType_ST){
> m_stores++;
> } else {
> // ERROR_MSG("Trying to add invalid access to trace");
> }
96,98c94,96
< if (access_mode == AccessModeType_UserMode) {
< m_user++;
< }
---
> if (access_mode == AccessModeType_UserMode) {
> m_user++;
> }
100,102c98,100
< if (sharing_miss) {
< m_sharing++;
< }
---
> if (sharing_miss) {
> m_sharing++;
> }
105c103,104
< int AccessTraceForAddress::getTotal() const
---
> int
> AccessTraceForAddress::getTotal() const
107,111c106,110
< if (m_histogram_ptr == NULL) {
< return m_total;
< } else {
< return m_histogram_ptr->getTotal();
< }
---
> if (m_histogram_ptr == NULL) {
> return m_total;
> } else {
> return m_histogram_ptr->getTotal();
> }
114c113,114
< void AccessTraceForAddress::addSample(int value)
---
> void
> AccessTraceForAddress::addSample(int value)
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< assert(m_total == 0);
< if (m_histogram_ptr == NULL) {
< m_histogram_ptr = new Histogram;
< }
< m_histogram_ptr->add(value);
---
> assert(m_total == 0);
> if (m_histogram_ptr == NULL) {
> m_histogram_ptr = new Histogram;
> }
> m_histogram_ptr->add(value);
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<
< bool node_less_then_eq(const AccessTraceForAddress* n1, const AccessTraceForAddress* n2)
< {
< return (n1->getTotal() > n2->getTotal());
< }