1
2/*
3 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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39 * next cycle. And on the cycle boundary swap the two set of
40 * states.
41 *
42 */
43
44#ifndef Switch_H
45#define Switch_H
46
47#include "mem/ruby/common/Global.hh"
48#include "mem/gems_common/Vector.hh"
49
50class MessageBuffer;
51class PerfectSwitch;
52class NetDest;
53class SimpleNetwork;
54class Throttle;

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63 void addInPort(const Vector<MessageBuffer*>& in);
64 void addOutPort(const Vector<MessageBuffer*>& out, const NetDest& routing_table_entry, int link_latency, int bw_multiplier);
65 const Throttle* getThrottle(LinkID link_number) const;
66 const Vector<Throttle*>* getThrottles() const;
67 void clearRoutingTables();
68 void clearBuffers();
69 void reconfigureOutPort(const NetDest& routing_table_entry);
70
71 void printStats(ostream& out) const;
72 void clearStats();
73 void printConfig(ostream& out) const;
74
75 // Destructor
76 ~Switch();
77
78 void print(ostream& out) const;
79private:
80
81 // Private copy constructor and assignment operator
82 Switch(const Switch& obj);
83 Switch& operator=(const Switch& obj);
84
85 // Data Members (m_ prefix)
86 PerfectSwitch* m_perfect_switch_ptr;
87 Network* m_network_ptr;
88 Vector<Throttle*> m_throttles;
89 Vector<MessageBuffer*> m_buffers_to_free;
90 SwitchID m_switch_id;
91};
92
93// Output operator declaration
94ostream& operator<<(ostream& out, const Switch& obj);
95
96// ******************* Definitions *******************
97
98// Output operator definition
99extern inline
100ostream& operator<<(ostream& out, const Switch& obj)
101{
102 obj.print(out);
103 out << flush;
104 return out;
105}
106
107#endif //Switch_H