1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
--- 13 unchanged lines hidden (view full) ---
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/*
30 * The actual modelled switch. It use the perfect switch and a
31 * Throttle object to control and bandwidth and timing *only for the
32 * output port*. So here we have un-realistic modelling, since the
33 * order of PerfectSwitch and Throttle objects get woke up affect the
34 * message timing. A more accurate model would be having two set of
35 * system states, one for this cycle, one for next cycle. And on the
36 * cycle boundary swap the two set of states.
37 */
38
39#ifndef __MEM_RUBY_NETWORK_SIMPLE_SWITCH_HH__
40#define __MEM_RUBY_NETWORK_SIMPLE_SWITCH_HH__
41
42#include <iostream>
43
44#include "mem/gems_common/Vector.hh"
45#include "mem/ruby/common/Global.hh"
46
47class MessageBuffer;
48class PerfectSwitch;
49class NetDest;
50class SimpleNetwork;
51class Throttle;
52class Network;
53
54class Switch
55{
56 public:
57 Switch(SwitchID sid, SimpleNetwork* network_ptr);
58 ~Switch();
59
60 void addInPort(const Vector<MessageBuffer*>& in);
61 void addOutPort(const Vector<MessageBuffer*>& out,
62 const NetDest& routing_table_entry, int link_latency,
63 int bw_multiplier);
64 const Throttle* getThrottle(LinkID link_number) const;
65 const Vector<Throttle*>* getThrottles() const;
66 void clearRoutingTables();
67 void clearBuffers();
68 void reconfigureOutPort(const NetDest& routing_table_entry);
69
70 void printStats(std::ostream& out) const;
71 void clearStats();
72 void printConfig(std::ostream& out) const;
73
74 void print(std::ostream& out) const;
75
76 private:
77 // Private copy constructor and assignment operator
78 Switch(const Switch& obj);
79 Switch& operator=(const Switch& obj);
80
81 PerfectSwitch* m_perfect_switch_ptr;
82 Network* m_network_ptr;
83 Vector<Throttle*> m_throttles;
84 Vector<MessageBuffer*> m_buffers_to_free;
85 SwitchID m_switch_id;
86};
87
88inline std::ostream&
89operator<<(std::ostream& out, const Switch& obj)
90{
91 obj.print(out);
92 out << std::flush;
93 return out;
94}
95
96#endif // __MEM_RUBY_NETWORK_SIMPLE_SWITCH_HH__
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
--- 13 unchanged lines hidden (view full) ---
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/*
30 * The actual modelled switch. It use the perfect switch and a
31 * Throttle object to control and bandwidth and timing *only for the
32 * output port*. So here we have un-realistic modelling, since the
33 * order of PerfectSwitch and Throttle objects get woke up affect the
34 * message timing. A more accurate model would be having two set of
35 * system states, one for this cycle, one for next cycle. And on the
36 * cycle boundary swap the two set of states.
37 */
38
39#ifndef __MEM_RUBY_NETWORK_SIMPLE_SWITCH_HH__
40#define __MEM_RUBY_NETWORK_SIMPLE_SWITCH_HH__
41
42#include <iostream>
43
44#include "mem/gems_common/Vector.hh"
45#include "mem/ruby/common/Global.hh"
46
47class MessageBuffer;
48class PerfectSwitch;
49class NetDest;
50class SimpleNetwork;
51class Throttle;
52class Network;
53
54class Switch
55{
56 public:
57 Switch(SwitchID sid, SimpleNetwork* network_ptr);
58 ~Switch();
59
60 void addInPort(const Vector<MessageBuffer*>& in);
61 void addOutPort(const Vector<MessageBuffer*>& out,
62 const NetDest& routing_table_entry, int link_latency,
63 int bw_multiplier);
64 const Throttle* getThrottle(LinkID link_number) const;
65 const Vector<Throttle*>* getThrottles() const;
66 void clearRoutingTables();
67 void clearBuffers();
68 void reconfigureOutPort(const NetDest& routing_table_entry);
69
70 void printStats(std::ostream& out) const;
71 void clearStats();
72 void printConfig(std::ostream& out) const;
73
74 void print(std::ostream& out) const;
75
76 private:
77 // Private copy constructor and assignment operator
78 Switch(const Switch& obj);
79 Switch& operator=(const Switch& obj);
80
81 PerfectSwitch* m_perfect_switch_ptr;
82 Network* m_network_ptr;
83 Vector<Throttle*> m_throttles;
84 Vector<MessageBuffer*> m_buffers_to_free;
85 SwitchID m_switch_id;
86};
87
88inline std::ostream&
89operator<<(std::ostream& out, const Switch& obj)
90{
91 obj.print(out);
92 out << std::flush;
93 return out;
94}
95
96#endif // __MEM_RUBY_NETWORK_SIMPLE_SWITCH_HH__