1 2/* 3 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; 10 * redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution; 13 * neither the name of the copyright holders nor the names of its 14 * contributors may be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30/* 31 * SimpleNetwork.hh 32 * 33 * Description: The SimpleNetwork class implements the interconnection 34 * SimpleNetwork between components (processor/cache components and 35 * memory/directory components). The interconnection network as 36 * described here is not a physical network, but a programming concept 37 * used to implement all communication between components. Thus parts 38 * of this 'network' may model the on-chip connections between cache 39 * controllers and directory controllers as well as the links between 40 * chip and network switches. 41 * 42 * Two conceptual networks, an address and data network, are modeled. 43 * The data network is unordered, where the address network provides 44 * and conforms to a global ordering of all transactions. 45 * 46 * Currently the data network is point-to-point and the address 47 * network is a broadcast network. These two distinct conceptual 48 * network can be modeled as physically separate networks or 49 * multiplexed over a single physical network. 50 * 51 * The network encapsulates all notion of virtual global time and is 52 * responsible for ordering the network transactions received. This 53 * hides all of these ordering details from the processor/cache and 54 * directory/memory modules. 55 * 56 * FIXME: Various flavor of networks are provided as a compiler time 57 * configurable. We currently include this SimpleNetwork in the 58 * makefile's vpath, so that SimpleNetwork.cc can provide an alternative 59 * version constructor for the abstract Network class. It is easy to 60 * modify this to make network a runtime configuable. Just make the 61 * abstract Network class take a enumeration parameter, and based on 62 * that to initial proper network. Or even better, just make the ruby 63 * system initializer choose the proper network to initiate. 64 * 65 * $Id$ 66 * 67 */ 68 69#ifndef SIMPLENETWORK_H 70#define SIMPLENETWORK_H 71 72#include "mem/ruby/common/Global.hh" 73#include "mem/gems_common/Vector.hh" 74#include "mem/ruby/network/Network.hh" 75#include "mem/ruby/system/NodeID.hh"
| 1 2/* 3 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; 10 * redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution; 13 * neither the name of the copyright holders nor the names of its 14 * contributors may be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30/* 31 * SimpleNetwork.hh 32 * 33 * Description: The SimpleNetwork class implements the interconnection 34 * SimpleNetwork between components (processor/cache components and 35 * memory/directory components). The interconnection network as 36 * described here is not a physical network, but a programming concept 37 * used to implement all communication between components. Thus parts 38 * of this 'network' may model the on-chip connections between cache 39 * controllers and directory controllers as well as the links between 40 * chip and network switches. 41 * 42 * Two conceptual networks, an address and data network, are modeled. 43 * The data network is unordered, where the address network provides 44 * and conforms to a global ordering of all transactions. 45 * 46 * Currently the data network is point-to-point and the address 47 * network is a broadcast network. These two distinct conceptual 48 * network can be modeled as physically separate networks or 49 * multiplexed over a single physical network. 50 * 51 * The network encapsulates all notion of virtual global time and is 52 * responsible for ordering the network transactions received. This 53 * hides all of these ordering details from the processor/cache and 54 * directory/memory modules. 55 * 56 * FIXME: Various flavor of networks are provided as a compiler time 57 * configurable. We currently include this SimpleNetwork in the 58 * makefile's vpath, so that SimpleNetwork.cc can provide an alternative 59 * version constructor for the abstract Network class. It is easy to 60 * modify this to make network a runtime configuable. Just make the 61 * abstract Network class take a enumeration parameter, and based on 62 * that to initial proper network. Or even better, just make the ruby 63 * system initializer choose the proper network to initiate. 64 * 65 * $Id$ 66 * 67 */ 68 69#ifndef SIMPLENETWORK_H 70#define SIMPLENETWORK_H 71 72#include "mem/ruby/common/Global.hh" 73#include "mem/gems_common/Vector.hh" 74#include "mem/ruby/network/Network.hh" 75#include "mem/ruby/system/NodeID.hh"
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| 76#include "sim/sim_object.hh" 77#include "params/SimpleNetwork.hh"
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76 77class NetDest; 78class MessageBuffer; 79class Throttle; 80class Switch; 81class Topology; 82 83class SimpleNetwork : public Network { 84public: 85 // Constructors
| 78 79class NetDest; 80class MessageBuffer; 81class Throttle; 82class Switch; 83class Topology; 84 85class SimpleNetwork : public Network { 86public: 87 // Constructors
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86 // SimpleNetwork(int nodes); 87 SimpleNetwork(const string & name);
| 88 typedef SimpleNetworkParams Params; 89 SimpleNetwork(const Params *p);
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88 89 // Destructor 90 ~SimpleNetwork(); 91
| 90 91 // Destructor 92 ~SimpleNetwork(); 93
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92 void init(const vector<string> & argv);
| 94 void init();
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93 94 // Public Methods 95 void printStats(ostream& out) const; 96 void clearStats(); 97 void printConfig(ostream& out) const; 98 99 void reset(); 100 101 // returns the queue requested for the given component 102 MessageBuffer* getToNetQueue(NodeID id, bool ordered, int network_num); 103 MessageBuffer* getFromNetQueue(NodeID id, bool ordered, int network_num); 104 virtual const Vector<Throttle*>* getThrottles(NodeID id) const; 105 106 bool isVNetOrdered(int vnet) { return m_ordered[vnet]; } 107 bool validVirtualNetwork(int vnet) { return m_in_use[vnet]; } 108 109 int getNumNodes() {return m_nodes; } 110 111 // Methods used by Topology to setup the network 112 void makeOutLink(SwitchID src, NodeID dest, const NetDest& routing_table_entry, int link_latency, int link_weight, int bw_multiplier, bool isReconfiguration); 113 void makeInLink(SwitchID src, NodeID dest, const NetDest& routing_table_entry, int link_latency, int bw_multiplier, bool isReconfiguration); 114 void makeInternalLink(SwitchID src, NodeID dest, const NetDest& routing_table_entry, int link_latency, int link_weight, int bw_multiplier, bool isReconfiguration); 115 116 void print(ostream& out) const; 117private: 118 void checkNetworkAllocation(NodeID id, bool ordered, int network_num); 119 void addLink(SwitchID src, SwitchID dest, int link_latency); 120 void makeLink(SwitchID src, SwitchID dest, const NetDest& routing_table_entry, int link_latency); 121 SwitchID createSwitch(); 122 void makeTopology(); 123 void linkTopology(); 124 125 126 // Private copy constructor and assignment operator 127 SimpleNetwork(const SimpleNetwork& obj); 128 SimpleNetwork& operator=(const SimpleNetwork& obj); 129 130 // Data Members (m_ prefix) 131 132 // vector of queues from the components 133 Vector<Vector<MessageBuffer*> > m_toNetQueues; 134 Vector<Vector<MessageBuffer*> > m_fromNetQueues; 135 136 Vector<bool> m_in_use; 137 Vector<bool> m_ordered; 138 Vector<Switch*> m_switch_ptr_vector; 139 Vector<MessageBuffer*> m_buffers_to_free; 140 Vector<Switch*> m_endpoint_switches; 141}; 142 143// Output operator declaration 144ostream& operator<<(ostream& out, const SimpleNetwork& obj); 145 146// ******************* Definitions ******************* 147 148// Output operator definition 149extern inline 150ostream& operator<<(ostream& out, const SimpleNetwork& obj) 151{ 152 obj.print(out); 153 out << flush; 154 return out; 155} 156 157#endif //SIMPLENETWORK_H
| 95 96 // Public Methods 97 void printStats(ostream& out) const; 98 void clearStats(); 99 void printConfig(ostream& out) const; 100 101 void reset(); 102 103 // returns the queue requested for the given component 104 MessageBuffer* getToNetQueue(NodeID id, bool ordered, int network_num); 105 MessageBuffer* getFromNetQueue(NodeID id, bool ordered, int network_num); 106 virtual const Vector<Throttle*>* getThrottles(NodeID id) const; 107 108 bool isVNetOrdered(int vnet) { return m_ordered[vnet]; } 109 bool validVirtualNetwork(int vnet) { return m_in_use[vnet]; } 110 111 int getNumNodes() {return m_nodes; } 112 113 // Methods used by Topology to setup the network 114 void makeOutLink(SwitchID src, NodeID dest, const NetDest& routing_table_entry, int link_latency, int link_weight, int bw_multiplier, bool isReconfiguration); 115 void makeInLink(SwitchID src, NodeID dest, const NetDest& routing_table_entry, int link_latency, int bw_multiplier, bool isReconfiguration); 116 void makeInternalLink(SwitchID src, NodeID dest, const NetDest& routing_table_entry, int link_latency, int link_weight, int bw_multiplier, bool isReconfiguration); 117 118 void print(ostream& out) const; 119private: 120 void checkNetworkAllocation(NodeID id, bool ordered, int network_num); 121 void addLink(SwitchID src, SwitchID dest, int link_latency); 122 void makeLink(SwitchID src, SwitchID dest, const NetDest& routing_table_entry, int link_latency); 123 SwitchID createSwitch(); 124 void makeTopology(); 125 void linkTopology(); 126 127 128 // Private copy constructor and assignment operator 129 SimpleNetwork(const SimpleNetwork& obj); 130 SimpleNetwork& operator=(const SimpleNetwork& obj); 131 132 // Data Members (m_ prefix) 133 134 // vector of queues from the components 135 Vector<Vector<MessageBuffer*> > m_toNetQueues; 136 Vector<Vector<MessageBuffer*> > m_fromNetQueues; 137 138 Vector<bool> m_in_use; 139 Vector<bool> m_ordered; 140 Vector<Switch*> m_switch_ptr_vector; 141 Vector<MessageBuffer*> m_buffers_to_free; 142 Vector<Switch*> m_endpoint_switches; 143}; 144 145// Output operator declaration 146ostream& operator<<(ostream& out, const SimpleNetwork& obj); 147 148// ******************* Definitions ******************* 149 150// Output operator definition 151extern inline 152ostream& operator<<(ostream& out, const SimpleNetwork& obj) 153{ 154 obj.print(out); 155 out << flush; 156 return out; 157} 158 159#endif //SIMPLENETWORK_H
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