1
2/*
3 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;

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23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/*
31 * SimpleNetwork.hh
32 *
33 * Description: The SimpleNetwork class implements the interconnection
34 * SimpleNetwork between components (processor/cache components and
35 * memory/directory components). The interconnection network as
36 * described here is not a physical network, but a programming concept
37 * used to implement all communication between components. Thus parts
38 * of this 'network' may model the on-chip connections between cache
39 * controllers and directory controllers as well as the links between
40 * chip and network switches.
41 *

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56 * FIXME: Various flavor of networks are provided as a compiler time
57 * configurable. We currently include this SimpleNetwork in the
58 * makefile's vpath, so that SimpleNetwork.cc can provide an alternative
59 * version constructor for the abstract Network class. It is easy to
60 * modify this to make network a runtime configuable. Just make the
61 * abstract Network class take a enumeration parameter, and based on
62 * that to initial proper network. Or even better, just make the ruby
63 * system initializer choose the proper network to initiate.
64 *
65 * $Id$
66 *
67 */
68
69#ifndef SIMPLENETWORK_H
70#define SIMPLENETWORK_H
71
72#include "mem/ruby/common/Global.hh"
73#include "mem/gems_common/Vector.hh"
74#include "mem/ruby/network/Network.hh"
75#include "mem/ruby/system/NodeID.hh"
76#include "sim/sim_object.hh"
77#include "params/SimpleNetwork.hh"
78
79class NetDest;
80class MessageBuffer;
81class Throttle;
82class Switch;
83class Topology;
84
85class SimpleNetwork : public Network {
86public:
87 // Constructors
88 typedef SimpleNetworkParams Params;
89 SimpleNetwork(const Params *p);
90
91 // Destructor
92 ~SimpleNetwork();
93
94 void init();
95
96 // Public Methods
97 void printStats(ostream& out) const;
98 void clearStats();
99 void printConfig(ostream& out) const;
100
101 void reset();
102
103 // returns the queue requested for the given component
104 MessageBuffer* getToNetQueue(NodeID id, bool ordered, int network_num);
105 MessageBuffer* getFromNetQueue(NodeID id, bool ordered, int network_num);
106 virtual const Vector<Throttle*>* getThrottles(NodeID id) const;
107
108 bool isVNetOrdered(int vnet) { return m_ordered[vnet]; }
109 bool validVirtualNetwork(int vnet) { return m_in_use[vnet]; }
110
111 int getNumNodes() {return m_nodes; }
112
113 // Methods used by Topology to setup the network
114 void makeOutLink(SwitchID src, NodeID dest, const NetDest& routing_table_entry, int link_latency, int link_weight, int bw_multiplier, bool isReconfiguration);
115 void makeInLink(SwitchID src, NodeID dest, const NetDest& routing_table_entry, int link_latency, int bw_multiplier, bool isReconfiguration);
116 void makeInternalLink(SwitchID src, NodeID dest, const NetDest& routing_table_entry, int link_latency, int link_weight, int bw_multiplier, bool isReconfiguration);
117
118 void print(ostream& out) const;
119private:
120 void checkNetworkAllocation(NodeID id, bool ordered, int network_num);
121 void addLink(SwitchID src, SwitchID dest, int link_latency);
122 void makeLink(SwitchID src, SwitchID dest, const NetDest& routing_table_entry, int link_latency);
123 SwitchID createSwitch();
124 void makeTopology();
125 void linkTopology();
126
127
128 // Private copy constructor and assignment operator
129 SimpleNetwork(const SimpleNetwork& obj);
130 SimpleNetwork& operator=(const SimpleNetwork& obj);
131
132 // Data Members (m_ prefix)
133
134 // vector of queues from the components
135 Vector<Vector<MessageBuffer*> > m_toNetQueues;
136 Vector<Vector<MessageBuffer*> > m_fromNetQueues;
137
138 Vector<bool> m_in_use;
139 Vector<bool> m_ordered;
140 Vector<Switch*> m_switch_ptr_vector;
141 Vector<MessageBuffer*> m_buffers_to_free;
142 Vector<Switch*> m_endpoint_switches;
143};
144
145// Output operator declaration
146ostream& operator<<(ostream& out, const SimpleNetwork& obj);
147
148// ******************* Definitions *******************
149
150// Output operator definition
151extern inline
152ostream& operator<<(ostream& out, const SimpleNetwork& obj)
153{
154 obj.print(out);
155 out << flush;
156 return out;
157}
158
159#endif //SIMPLENETWORK_H