1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <cassert>
30#include <numeric>
31
32#include "base/cast.hh"
33#include "base/stl_helpers.hh"
34#include "mem/ruby/common/NetDest.hh"
35#include "mem/ruby/network/MessageBuffer.hh"
36#include "mem/ruby/network/simple/SimpleLink.hh"
37#include "mem/ruby/network/simple/SimpleNetwork.hh"
38#include "mem/ruby/network/simple/Switch.hh"
39#include "mem/ruby/network/simple/Throttle.hh"
40#include "mem/ruby/profiler/Profiler.hh"
41
42using namespace std;
43using m5::stl_helpers::deletePointers;
44
45SimpleNetwork::SimpleNetwork(const Params *p)
46 : Network(p), m_buffer_size(p->buffer_size),
47 m_endpoint_bandwidth(p->endpoint_bandwidth),
48 m_adaptive_routing(p->adaptive_routing)
49{
50 // record the routers
51 for (vector<BasicRouter*>::const_iterator i = p->routers.begin();
52 i != p->routers.end(); ++i) {
53 Switch* s = safe_cast<Switch*>(*i);
54 m_switches.push_back(s);
55 s->init_net_ptr(this);
56 }
57
58 m_int_link_buffers = p->int_link_buffers;
59 m_num_connected_buffers = 0;
60}
61
62void
63SimpleNetwork::init()
64{
65 Network::init();
66
67 // The topology pointer should have already been initialized in
68 // the parent class network constructor.
69 assert(m_topology_ptr != NULL);
70 m_topology_ptr->createLinks(this);
71}
72
73SimpleNetwork::~SimpleNetwork()
74{
75 deletePointers(m_switches);
76 deletePointers(m_int_link_buffers);
77}
78
79// From a switch to an endpoint node
80void
81SimpleNetwork::makeExtOutLink(SwitchID src, NodeID dest, BasicLink* link,
82 const NetDest& routing_table_entry)
83{
84 assert(dest < m_nodes);
85 assert(src < m_switches.size());
86 assert(m_switches[src] != NULL);
87
88 SimpleExtLink *simple_link = safe_cast<SimpleExtLink*>(link);
89
90 m_switches[src]->addOutPort(m_fromNetQueues[dest], routing_table_entry,
91 simple_link->m_latency,
92 simple_link->m_bw_multiplier);
93}
94
95// From an endpoint node to a switch
96void
97SimpleNetwork::makeExtInLink(NodeID src, SwitchID dest, BasicLink* link,
98 const NetDest& routing_table_entry)
99{
100 assert(src < m_nodes);
101 m_switches[dest]->addInPort(m_toNetQueues[src]);
102}
103
104// From a switch to a switch
105void
106SimpleNetwork::makeInternalLink(SwitchID src, SwitchID dest, BasicLink* link,
| 1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <cassert>
30#include <numeric>
31
32#include "base/cast.hh"
33#include "base/stl_helpers.hh"
34#include "mem/ruby/common/NetDest.hh"
35#include "mem/ruby/network/MessageBuffer.hh"
36#include "mem/ruby/network/simple/SimpleLink.hh"
37#include "mem/ruby/network/simple/SimpleNetwork.hh"
38#include "mem/ruby/network/simple/Switch.hh"
39#include "mem/ruby/network/simple/Throttle.hh"
40#include "mem/ruby/profiler/Profiler.hh"
41
42using namespace std;
43using m5::stl_helpers::deletePointers;
44
45SimpleNetwork::SimpleNetwork(const Params *p)
46 : Network(p), m_buffer_size(p->buffer_size),
47 m_endpoint_bandwidth(p->endpoint_bandwidth),
48 m_adaptive_routing(p->adaptive_routing)
49{
50 // record the routers
51 for (vector<BasicRouter*>::const_iterator i = p->routers.begin();
52 i != p->routers.end(); ++i) {
53 Switch* s = safe_cast<Switch*>(*i);
54 m_switches.push_back(s);
55 s->init_net_ptr(this);
56 }
57
58 m_int_link_buffers = p->int_link_buffers;
59 m_num_connected_buffers = 0;
60}
61
62void
63SimpleNetwork::init()
64{
65 Network::init();
66
67 // The topology pointer should have already been initialized in
68 // the parent class network constructor.
69 assert(m_topology_ptr != NULL);
70 m_topology_ptr->createLinks(this);
71}
72
73SimpleNetwork::~SimpleNetwork()
74{
75 deletePointers(m_switches);
76 deletePointers(m_int_link_buffers);
77}
78
79// From a switch to an endpoint node
80void
81SimpleNetwork::makeExtOutLink(SwitchID src, NodeID dest, BasicLink* link,
82 const NetDest& routing_table_entry)
83{
84 assert(dest < m_nodes);
85 assert(src < m_switches.size());
86 assert(m_switches[src] != NULL);
87
88 SimpleExtLink *simple_link = safe_cast<SimpleExtLink*>(link);
89
90 m_switches[src]->addOutPort(m_fromNetQueues[dest], routing_table_entry,
91 simple_link->m_latency,
92 simple_link->m_bw_multiplier);
93}
94
95// From an endpoint node to a switch
96void
97SimpleNetwork::makeExtInLink(NodeID src, SwitchID dest, BasicLink* link,
98 const NetDest& routing_table_entry)
99{
100 assert(src < m_nodes);
101 m_switches[dest]->addInPort(m_toNetQueues[src]);
102}
103
104// From a switch to a switch
105void
106SimpleNetwork::makeInternalLink(SwitchID src, SwitchID dest, BasicLink* link,
|
108{
109 // Create a set of new MessageBuffers
110 std::vector<MessageBuffer*> queues(m_virtual_networks);
111
112 for (int i = 0; i < m_virtual_networks; i++) {
113 // allocate a buffer
114 assert(m_num_connected_buffers < m_int_link_buffers.size());
115 MessageBuffer* buffer_ptr = m_int_link_buffers[m_num_connected_buffers];
116 m_num_connected_buffers++;
117 queues[i] = buffer_ptr;
118 }
119
120 // Connect it to the two switches
121 SimpleIntLink *simple_link = safe_cast<SimpleIntLink*>(link);
122
123 m_switches[dest]->addInPort(queues);
124 m_switches[src]->addOutPort(queues, routing_table_entry,
125 simple_link->m_latency,
126 simple_link->m_bw_multiplier);
127}
128
129void
130SimpleNetwork::regStats()
131{
132 Network::regStats();
133
134 for (MessageSizeType type = MessageSizeType_FIRST;
135 type < MessageSizeType_NUM; ++type) {
136 m_msg_counts[(unsigned int) type]
137 .name(name() + ".msg_count." + MessageSizeType_to_string(type))
138 .flags(Stats::nozero)
139 ;
140 m_msg_bytes[(unsigned int) type]
141 .name(name() + ".msg_byte." + MessageSizeType_to_string(type))
142 .flags(Stats::nozero)
143 ;
144
145 // Now state what the formula is.
146 for (int i = 0; i < m_switches.size(); i++) {
147 m_msg_counts[(unsigned int) type] +=
148 sum(m_switches[i]->getMsgCount(type));
149 }
150
151 m_msg_bytes[(unsigned int) type] =
152 m_msg_counts[(unsigned int) type] * Stats::constant(
153 Network::MessageSizeType_to_int(type));
154 }
155}
156
157void
158SimpleNetwork::collateStats()
159{
160 for (int i = 0; i < m_switches.size(); i++) {
161 m_switches[i]->collateStats();
162 }
163}
164
165void
166SimpleNetwork::print(ostream& out) const
167{
168 out << "[SimpleNetwork]";
169}
170
171SimpleNetwork *
172SimpleNetworkParams::create()
173{
174 return new SimpleNetwork(this);
175}
176
177/*
178 * The simple network has an array of switches. These switches have buffers
179 * that need to be accessed for functional reads and writes. Also the links
180 * between different switches have buffers that need to be accessed.
181 */
182bool
183SimpleNetwork::functionalRead(Packet *pkt)
184{
185 for (unsigned int i = 0; i < m_switches.size(); i++) {
186 if (m_switches[i]->functionalRead(pkt)) {
187 return true;
188 }
189 }
190
191 return false;
192}
193
194uint32_t
195SimpleNetwork::functionalWrite(Packet *pkt)
196{
197 uint32_t num_functional_writes = 0;
198
199 for (unsigned int i = 0; i < m_switches.size(); i++) {
200 num_functional_writes += m_switches[i]->functionalWrite(pkt);
201 }
202
203 for (unsigned int i = 0; i < m_int_link_buffers.size(); ++i) {
204 num_functional_writes += m_int_link_buffers[i]->functionalWrite(pkt);
205 }
206 return num_functional_writes;
207}
| 110{
111 // Create a set of new MessageBuffers
112 std::vector<MessageBuffer*> queues(m_virtual_networks);
113
114 for (int i = 0; i < m_virtual_networks; i++) {
115 // allocate a buffer
116 assert(m_num_connected_buffers < m_int_link_buffers.size());
117 MessageBuffer* buffer_ptr = m_int_link_buffers[m_num_connected_buffers];
118 m_num_connected_buffers++;
119 queues[i] = buffer_ptr;
120 }
121
122 // Connect it to the two switches
123 SimpleIntLink *simple_link = safe_cast<SimpleIntLink*>(link);
124
125 m_switches[dest]->addInPort(queues);
126 m_switches[src]->addOutPort(queues, routing_table_entry,
127 simple_link->m_latency,
128 simple_link->m_bw_multiplier);
129}
130
131void
132SimpleNetwork::regStats()
133{
134 Network::regStats();
135
136 for (MessageSizeType type = MessageSizeType_FIRST;
137 type < MessageSizeType_NUM; ++type) {
138 m_msg_counts[(unsigned int) type]
139 .name(name() + ".msg_count." + MessageSizeType_to_string(type))
140 .flags(Stats::nozero)
141 ;
142 m_msg_bytes[(unsigned int) type]
143 .name(name() + ".msg_byte." + MessageSizeType_to_string(type))
144 .flags(Stats::nozero)
145 ;
146
147 // Now state what the formula is.
148 for (int i = 0; i < m_switches.size(); i++) {
149 m_msg_counts[(unsigned int) type] +=
150 sum(m_switches[i]->getMsgCount(type));
151 }
152
153 m_msg_bytes[(unsigned int) type] =
154 m_msg_counts[(unsigned int) type] * Stats::constant(
155 Network::MessageSizeType_to_int(type));
156 }
157}
158
159void
160SimpleNetwork::collateStats()
161{
162 for (int i = 0; i < m_switches.size(); i++) {
163 m_switches[i]->collateStats();
164 }
165}
166
167void
168SimpleNetwork::print(ostream& out) const
169{
170 out << "[SimpleNetwork]";
171}
172
173SimpleNetwork *
174SimpleNetworkParams::create()
175{
176 return new SimpleNetwork(this);
177}
178
179/*
180 * The simple network has an array of switches. These switches have buffers
181 * that need to be accessed for functional reads and writes. Also the links
182 * between different switches have buffers that need to be accessed.
183 */
184bool
185SimpleNetwork::functionalRead(Packet *pkt)
186{
187 for (unsigned int i = 0; i < m_switches.size(); i++) {
188 if (m_switches[i]->functionalRead(pkt)) {
189 return true;
190 }
191 }
192
193 return false;
194}
195
196uint32_t
197SimpleNetwork::functionalWrite(Packet *pkt)
198{
199 uint32_t num_functional_writes = 0;
200
201 for (unsigned int i = 0; i < m_switches.size(); i++) {
202 num_functional_writes += m_switches[i]->functionalWrite(pkt);
203 }
204
205 for (unsigned int i = 0; i < m_int_link_buffers.size(); ++i) {
206 num_functional_writes += m_int_link_buffers[i]->functionalWrite(pkt);
207 }
208 return num_functional_writes;
209}
|